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參數(shù)資料
| 型號： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴展頻譜收發(fā)器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大小： | 220K |
| 代理商： | W9310 |
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W9310
- 8 -
Pin Description, continued
SYMBOL
MODOUT
PIN
71
I/O
O
FUNCTION
Modulation output. Spread spectrum modulated chip output. A tri-
state output that is in high impedance when TXEN is low.
Received data input. CMOS compatible input from analog
receiver.
Reset 1. When low, resets the storage elements in the W9310
and freezes all clocks except the master oscillator.
Reset 2. Resets the entire W9310 except the SBI.
DI
78
I
RST1_N
40
I
RST2_N
SBI Circuit Signals
SDI
41
I
64
I
SBI data input. Used by the microprocessor to write data into the
W9310.
SBI data output. Tri-state output pin. It is in high-impedance state
unless CHIPSEL_N is low and ADDR is set to 0 or 1.
SBI clock. Serial clock delivered to the W9310 by the
microprocessor when reading or writing. When idle, it should be
kept high.
SBI latch. Latch signal used by the microprocessor to latch in the
serial input data or to reset the interrupts
Chip select. When low, validates the address on the address bus.
When high, the W9310 ignores all activity on the address bus.
SBI address bus. MSB is bit 3, LSB is bit 0. Used to select the
SBI register for reading or writing. When SBI is not being
accessed, ADDR should be set to an unused address (for
example, hex 15).
SBI Interrupt 1. Indicates that a status nibble is available for
reading.
SBI Interrupt 2. Indicates that S/N data are available for reading.
SDO
44
O
SCLK
62
I
LATCH
61
I
CHIPSEL_
N
ADDR[0:3]
60
I
56, 55,
54, 53
I
IRQ1_N
43
O
IRQ2_N
Test Circuit Signals
EPX[0:6]
45
O
5, 6, 16,
17, 18,
21, 25
I, O
Exponent X. When set as outputs, delivers the output of the
correlators A & B (time multiplexed). When set as inputs,
replaces correlators A & B as data source to acquisition section of
the receive module. Bit 6 is MSB, bit 0 is LSB.
Exponent Y. When set to outputs, delivers the output of the
correlators C & D (time multiplexed). When set to inputs, replaces
correlators C & D as data source to acquisition section of the
receive module. Bit 6 is MSB, bit 0 is LSB.
Extra 8 KHz. External clock input for testing use.
Extra clock. External clock input for testing use. It clocks the test
counter among other modules.
EPY[0:6]
36, 46,
57, 58,
59, 65
I, O
X8KHZ
XTRACLK
9
10
I
I
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