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參數資料
| 型號： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴展頻譜收發器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數： | 25/36頁 |
| 文件大小： | 220K |
| 代理商： | W9310 |
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W9310
Publication Release Date: July 1996
- 25 -
Revision A3
BURST_CLK
TXEN
RFPWR
Tburst_clk
Tburst_clk
Figure 10. RFPWR Timing
TXEN
PLLSW
Receive
Receive
Transmit
Not drawn to scale.
27xTburst_clk
Tburst_clk
Figure 11. PLLSW Timing (Full-duplex Mode)
The PLLSW is asserted 27 burst clock cycles(duration of G1) prior to TXEN assertion and is de-
asserted 1 burst clock cycle prior to when TXEN is de-asserted. Thus, for a master oscillator of
16.384 MHz (corresponding to a burst rate of 85.333 KHz or a burst period of 11.72
μ
S), the PLLSW
signal will be asserted 316.44
μ
S (27*11.72 = 316.44) prior to TXEN assertion.
The RFPWR switch timing is designed to avoid damage to the sensitive analog receiver. When
switching from receive to transmit, RFPWR is delayed relative to TXEN (which can be used for
switching the antenna between transmit and receive chain) to ensure that the receiver has been
turned off before the transmitter is turned on. Similarly, when switching from transmit to receive,
RFPWR is turned off before TXEN to allow for extra time for the transmitter to turn off prior to turning
on the receiver circuits.
The PLLSW signal is designed to switch the RF PLL when different frequencies are used for transmit
and receive operations. In this instance, PLLSW is turned on at the end of receive operation and prior
to TXEN assertion to allow the RF PLL to stabilize. Similarly, the PLLSW changes to a low as soon as
transmission is finished and before reception commences.
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