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參數資料
型號: W88113C
廠商: WINBOND ELECTRONICS CORP
英文描述: ATAPI CD-ROM DECODER & CONTROLLER
中文描述: ATAPI的CD - ROM解碼器
文件頁數: 19/102頁
文件大小: 573K
代理商: W88113C
W88113C
Publication Release Date: Mar. 1999
- 15 - Revision 0.61
Bit 4:
HCIb - Host Command Interrupt Flag
This bit is activated by the following events:
Host issues ATAPI Soft Reset Command, if
ARSTIEN(2Fh.1)
is enabled
Host issues command to a non-exist slave drive, if
SHIEN(2Eh.2)
is enabled
Host issues Execute Drive Diagnostics Command, if
HIIEN(2Eh.7)
is enabled
ATAC(2Fh.6)
becomes active-high, if
HIIEN(2Eh.7)
is enabled
Host set bit SRST in ATAPI Device Control Register, if
HIIEN(2Eh.7)
is enabled
TBSYb - Transfer Busy Flag
This bit becomes active-low when the data transfer to host is triggered by the following
events:
Writing any value to register
THTRG (06h,w)
Setting bit
ADTT (17h.w2)
high
After host read the last byte to be transferred, this flag is deactivated.
APIb - Audio Playback Interrupt Flag
If
APOUT (90h,1-0)
are not zero, this bit is used as audio-playback-interrupt flag.
DFRDYb - Data FIFO Ready
After data transfer is triggered, the 32-byte Data FIFOs is automatically filled. This bit is used
to indicate that the Data FIFOs is ready to be read by the host for debugging. The Data FIFO
is automatically cleared in any of the following conditions:
Chip reset, host reset and firmware reset
DTEN (01h.w1)
is 0
DINB (1Fh.w1)
is 1
DFRST (2Bh.w3)
is 1
The end of data-in transfer
SCIb - Subcode Interrupt Flag
If
SCIEN (2Ch.w4)
is enabled, this bit becomes active-low when one of the following events
occurs:
ISS (22h.r0)
becomes active-high
NESBK (22h.r1)
becomes active-high
MSS (22h.r2)
becomes active-high
When Subcode Interrupt is activated, the microprocessor can read register
SUBSTA (22h,r)
to determine the reason of interrupt. Writing register
SCIACK (22h,w)
deactivates this flag
Bit 3:
Bit 2:
Bit 1:
Bit 0:
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