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參數(shù)資料
| 型號(hào)： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁(yè)數(shù)： | 31/102頁(yè) |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 27 - Revision 0.61
Bit 0:
DISAI - Disable Auto-Increment of Microprocessor-RAM Address Counter
When this bit is high, the automatic increment of the
RAC (2Dh/1Dh/1Ch)
address counter is
disabled. Note that DISAI should be 0 before
RFTRG (2Ah.w6)
is triggered.
SUBH0 to SUBH3 - Subheader Registers - (read 14h to 17h)
These registers are used to hold the information of subheader bytes. If
BUFEN (0Ah.w2)
is disabled,
subheader bytes are latched from incoming serial data. If
BUFEN (0Ah.w2)
is enabled, subheader
bytes are retrieved from the external RAM.
ASTRG - Automatic Sequence Trigger Register (write 17h)
The following bits will clear themselves after the triggered operation are completed.
Bit 7:
Reserved
Bit 6:
CSRT - Clear Soft Reset Trigger
Setting this bit high clears bit SRST in the ATAPI Device Control Register.
Bit 5:
DSCT - Disk Seek Complete Trigger
If
ABYEN (18h.1)
is high, setting
DSCT
high triggers the following operations:
Set BSY
DSC (37h.4)
←
1
Clear BSY
If
ABYEN (18h.1)
is low, setting
DSCT
high sets DSC(37h.4) to 1.
Bit 4:
SIGT - ATAPI Signature Trigger
Setting this bit high initialize the Task Registers with ATAPI signature.
ATFEA (31h)
←
00h
ATERR (31h)
←
01h
ATINT (32h)
←
01h
ATSPA (33h)
←
01h
ATBLO (34h)
←
14h
ATBHI (35h)
←
EBh
ATSTA (37h)
←
x00x0000b
Note that register ATDRS (36h) is not cleared by triggering SIGT to abide by the ATAPI protocol.
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|---|---|
| W88113CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
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| W88631F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
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