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參數資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數： | 30/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 26 - Revision 0.61
Bit 7:
MBVAb - Multi-Block Counter Valid Flag
This bit is used to indicate that
MBC (12h.4-0)
is stable enough to be monitored by
microprocessor. There is no need to monitor this bit in normal operation.
MBINC - Multi-Block Increment Flag
This bit becomes active-high if microprocessor sets
INCMBC (13h.w0)
and multi-block
number increment has not completed. There is no need to monitor this bit in normal
operation.
Bit 4-0: MBC[4:0] - Multi-Block Counter
Before triggering multi-block transfer, the number of blocks to be transferred minus 1 should
be written to
MBC (12h.4-0)
. Single block transfer is performed if
MBC (12h.4-0)
is zero.
There is no need to monitor this counter normal operation.
Bit 6:
MBTC1 - Multi-Block Transfer Control 1 - (read/write 13h)
This register is for debug only. This register is 0 after chip reset, host reset and firmware reset.
Bit 7-3: Reserved
Bit 2:
MBTIEN - Multi-Block Transfer Interrupt Enable
If
MBTIEN
and
MBTFEN
are both enabled,
pin UINTb (36)
will activate at the end of data
transfer of each block if the block count in
MBC (12h.4-0)
is not zero. There is no need to set
this bit in normal operation.
Bit 1:
MBTFEN - Multi-Block Transfer Interrupt Flag Enable
If this bit is high,
MBTI (30h.r4)
will be activated at the end of data transfer of each block if
the block count in
MBC (12h.4-0)
is not zero. There is no need to set this bit in normal
operation.
Bit 0:
INCMBC - Increment Multi-Block Counter
Setting this bit high increments
MBC (12h.4-0)
. This function is useful in data transfer to host
by DMA mode. Because data byte count is not specified in DMA mode transfer, the number
of block to be transferred can be incremented when a new block becomes available before
the transfer is completed.
ECTRL - Enhanced Control Register - (write 14h)
Bit 7-2: Reserved
Bit 1:
IR7F - Provide Flag UTBY at IR7
When this bit is high, flag
UTBY (1Fh.r7)
can be monitored by read bit-7 of the Index
Register.
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相關代理商/技術參數 |
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|---|---|
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