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參數資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數： | 50/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 46 - Revision 0.61
Bit 6:
CMDC - Command Conflict
This bit becomes high if one of the following events occurs while BSY is high:
Host writes any opcode to ATAPI Command Register while drive is selected.
Host writes any opcode to ATAPI Command Register while shadow drive is selected and
SHDRV (3Fh.6)
is enabled.
Host writes opcode 90h (Execute Drive Diagnostics) to ATAPI Command Register.
CMDC is updated each time the host writes the ATAPI Command Register.
TDIR - Data Transfer Direction
Bit 5:
TENDb
(01h.r6)
TDIR
(30h.r5)
FPKT
(30h.1)
Transfer End Reason
Acknowledge
register
0
1
0
data-in transfer
DHTACK (0Eh)
0
1
x
data-out transfer
TACK (07h)
0
0
x
A0 command packet transfer
TACK (07h)
Bit 4:
MBTI - Multi-block Transfer Interrupt
This flag indicates the end of each block transfer while the Multi-block transfer is used.
UCRCOKB
- Ultra DMA CRCOK/RAM Parity Interrupt Flag
This bit becomes high if an Ultra DMA CRC error is detected at the end of Ultra DMA burst.
CRST - Chip Reset Flag
This bit is set high by chip reset. The first read of register
MISS2 (30h,r)
following the end of
the chip reset clears this flag to 0.
FPKT -Full Packet Flag
This bit becomes high if the host has written the number of data bytes indicated in register
ATBLO (less than 12 bytes), or the host has written a 12-byte command packet. If CoD
(32h.0) is low when DRQ (37h.3) change from 0 to 1, the count in ATBLO is latched as a
threshold value for FPKT logic. If CoD is high when DRQ (37h.3) change from 0 to 1, the
threshold value of FPKT logic is set as 12. Whenever the number of bytes in the Packet
FIFO equals the threshold value, flag FPKT becomes high. To receive data from host using
Packet FIFO, CoD (32h.0) and ATBLO (32h) should be updated at rising edge of DRQ.
APKT - Automatic Packet Transfer Flag
This bit is set to 1 when host writes opcode A0h to ATA Command Register if drive is
selected and
APKTEN (18h.7)
has been enabled. When this flag is high, BSY is controlled
by the Automatic Packet Transfer logic. Hence, setting of
CLRBSY (20h.4)
and
SETBSY
(20h.4)
is of no effect. APKT is de-activated by writing any value to register
TACK (07h,w)
.
APKT is de-activated by chip reset or host reset but is not changed by firmware reset.
Bit 3:
Bit 2:
Bit 1:
Bit 0:
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相關代理商/技術參數 |
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