- 您現在的位置：買賣IC網 > PDF目錄363904 > W88113C (WINBOND ELECTRONICS CORP) ATAPI CD-ROM DECODER & CONTROLLER PDF資料下載
參數資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數： | 22/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
W88113C
Publication Release Date: Mar. 1999
- 18 - Revision 0.61
EIAL/EIAH - ECC Initial Address - (read 08h/09h, write 0Ch/0Dh)
EIAH/L are used to hold the initial address offset of the data block to be corrected. The content of
BIAH/L (09h/08h,w)
will be automatically loaded to
EIAH/L
at the beginning of each data sync,
making it unnecessary to read or write EIAH/L during normal operation. The RAM block for ECC is
controlled by the number in registers
DDBH/L (29h/28h)
.
CTRL0 - Control Register 0 - (write 0Ah)
This register is 0 after chip reset, host reset, firmware reset and decoder reset.
Bit 7:
DECEN - Decoding Logic Enable
Setting this bit high enables the decoding logic.
Bit 6:
RTEDC
- Real Time EDC Checking Enable
Setting this bit high enables the real-time-EDC-checking logic. The RSPC error correction is
performed only when the result of real time EDC check is error. This function could save
about 2/3 of DRAM bandwidth compared with conventional decoder.
Bit 5:
EDCEN - Error Detect and Correct Enable
Setting this bit high enables the ECC and EDC logic. Change of this bit takes effect after next
sync.
Bit 4:
ACEN - Automatic Correction Enable
If both
M2RQ (0Bh.w3)
and this bit is high, the type of error correction is automatically
determined by FORM bit in the subheader byte. If only
M2RQ (0Bh.w3)
is high, the type of
error correction is controlled by
F2RQ (0Bh.w2)
. If
M2RQ (0Bh.w3)
is low, this bit does not
affect the correction of mode 1 data.
Bit 3:
PKTINH - obsolete
Bit 2:
BUFEN - Buffering Enable
Setting this bit high enables incoming DSP data buffering. When this bit is high, the values
of register HEAD0-3(04h-07h) and SUBH0-3(14h-17h) are retrieved from external RAM rather
than from incoming serial data. When BUFEN is low, any setting of QCEN or PCEN is
meaningless. Change of this bit takes effect after next sync.
Bit 1:
QCEN - Q-codeword Correction Enable
When this bit is high, Q-codeword RSPC correction logic is enabled. Change of this bit takes
effect after next sync.
Bit 0:
PCEN - P-codeword Correction Enable
When this bit is high, P-codeword RSPC correction logic is enabled. Change of this bit takes
effect after next sync.
相關PDF資料 |
PDF描述 |
|---|---|
| W88113CD | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | ATAPI CD-ROM DECODER & CONTROLLER |
| W88227F | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| W88227QD | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| W88611P | VCD 4X RF Amplifer/Digital Servo & DSP(具有射頻運算放大器及數字信號伺服和處理的集成芯片) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W88113CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88611P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
| W88631F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
| W88980 | 制造商:Performance Tool 功能描述:Anti-Fatigue Floor Mat Roll - 12 Square Feet 制造商:PERFORMANCE TOOLS 功能描述:ANTI-FATIGUE FLOOR MAT ROLL 12 SQ FT |
發布緊急采購，3分鐘左右您將得到回復。