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參數資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數： | 27/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 23 - Revision 0.61
FRST - Firmware Reset Register - (write 0Fh)
Writing this register, regardless of what value is written, trigger a firmware reset. Flag
FRST (2Fh.r1)
is set by firmware reset.
STAT3 - Status Register 3 - (read 0Fh)
Bit 7:
STAVAb - Valid Status Valid
This bit is used to indicate that the header, pointer, and status registers about decoder logic
are available. This bit should not be used if
BICEN (9Ah.7)
is high.
Bit 5:
ECF - Error Corrected Flag
This bit is used to indicate that there is at least one byte was corrected in the latest available
block.
Bit 1:
C2DF - C2 Detected in Block Flag
If
C2WEN (10h.w2)
is high, C2DF becomes high when there is at least one C2PO flag was
detected in the previous block.
Bit 6,4,3,2,0: Reserved
CTRLW - Control-Write Register - (write 10h)
This register is 0 after chip reset, host reset, firmware reset and decoder reset.
Bit 7: reserved
Bit 6:
SWEN - Synchronized Write Enable
If this bit is high, the change of
BUFEN (0Ah.w2)
will be synchronized to the end of next
sector sync. The buffering of C2PO flags is also controlled by this bit if
C2WEN (10h.w2)
and
BUFEN (0AH.w2)
are both enabled. This function prevents buffering of an incomplete block.
Bit 5:
SDSS - Subcode and DSP Sync Synchronization
This bit provides synchronization of CD-DA format data. If this bit is high, the writing of
incoming serial data to the external RAM will start at the first left-channel lower-byte following
the end of subcode block. Note that this bit should not be used when subcode logic is not
enabled.
Bit 4:
DCKEN - DSP Clock Enable
If this bit is high, clock from DSP is used by internal decoder logic. DCKEN should be set
high
before
DECEN (0Ah.w7)
is set high.
Bit 3,0: reserved
Bit 2:
C2WEN - C2 Flag Write Enable
If this bit and
BUFEN (0Ah.w2)
are both high, the C2 flags of incoming serial data will be
latched into the external RAM. This operation is synchronized to the end of sync if
SWEN
(10h.w6)
is high.
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