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參數(shù)資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數(shù)： | 43/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 39 - Revision 0.61
Bit 5:
Bit 4:
Reserved (write only)
SWAP - Host High-Low Swap
Setting this bit high causes the host access of high/low byte to be swapped.
Reserved
Bit 2-0: RTC[2:0] - External RAM Type Configuration Bits
The external RAM should be appropriately configured by these three bits according to its
specification. RTC[2:0] are de-activated by chip reset or host reset, but are not changed by
firmware reset.
Bit 3:
RTC[2:0]
RAM Configuration
0,1, 4, 7
reserved
2
256K x 4-bit x 2, 256K x 8-bit x 1,
128K x 8-bit x 1, 8-Row 9-Column
3
128K x 8-bit x 1, 9-Row 8-Column
4
64K x 16-bit x 1, (8-row 8-Column)
128K x 16-bit x 1 (9-Row 8-Column)
128K x 8-bit x 2 (9-Row 8-Column)
5
256K x 16-bit x 1
128K x 16-bit x 1 (8-Row 9-Column)
128K x 8-bit x 2, (8-Row 9-Column)
6
1 M x 4-bit x 2
Note: The control bit
ALE2 (5Ch.3)
must be set while using 16-bit DRAM.
MEMCF - Memory Layout Configuration Register - (write 2Bh)
Bits 7-6: Reserved
Bits 5-4:
DBAF[1:0]
- DRAM Bus Arbitration Factor
The value in control bits
DBAF1-0 (2Bh.w5-4)
defines the DRAM bus arbitration factor,
daf
,
which can adjust the number of cycles between two host transfer pre-fetch cycles is at most
2
daf
. If less bandwidth is demanded by logic other than host transfer, the bandwidth is
automatically arbitrated to achieve the best performance. If The value in these bits is 0 after
chip reset and firmware reset.
Bit 3:
DFRST - Data FIFO Reset
Setting this bit high resets Data FIFO. This bit is not self-clear.
Bit 2:
FRDY - Fast Pin IORDY Enable
Setting this bit high accelerates the de-assertion of
pin IORDY (49)
without referring
pin
HRDb (50)
.
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