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參數(shù)資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數(shù)： | 42/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 38 - Revision 0.61
SCBH/L - Subcode Block Register - (read/write 27h/26h)
SCBH/L (27h/26h)
form a 9-bit counter that contains the block number of the latest available subcode
data that can be read by the host. The number in
SCBH/L (27h/26h)
plus 1 points to the RAM block
that is buffering incoming subcode. The number in
SCBH/L (27h/26h)
increments at the end of
subcode block buffering. If
SDBS (88h.4)
is high, the buffering of subcode is controlled by
DDBH/L
(29h/28h)
rather than
SCBH/L (27h/26h)
.
DDBH/L - Decoded Data Block Register - (read/write 29h/28h)
DDBH/L(29h/28h)
form a 9-bit counter that contains the number of the latest available decoded data
block after decoder interrupt occurs. CD-ROM sector data buffering is a block-based ring operation.
In
Real-Time-Correction (RTC)
mode, i.e.,
BICEN (9Ah.7)
is low, if the number in
DDBH/L (29h/28h)
is
N - 1
, then the current sector is buffered into block with number
N
. The
DDBH/L (29h/28h)
increments at each sync. When the decoded-block-number equals the value in
WBRCH/L (57h/56h)
,
the sector is buffered into the block with number specified by
WBRBH/L (55h/54h)
.
In
Buffer-Independent-Correction (BIC)
mode, i.e.,
BICEN (9Ah.7)
is low,
DDBH/L (29h/28h)
increments at the end of EDC-checking if there is no
STAERR (80h.r6)
or
HCEI (80h.r0)
error.
RAMCF - RAM Configuration Register - (read/write 2Ah)
This register is 0 after chip reset.
Bit 7:
RFTYP - Refresh Type
The refresh mode of DRAM is CAS-before-RAS if this bit is high. The refresh mode of DRAM
is RAS-only if this bit is low.
Bit 6:
RFTRG - RAM Filling Trigger
Setting this bit high triggers the DRAM filling. All locations in the external RAM will be filled
with the value in register
RAMWR (1Eh,w)
. The value (ex:00h) should be written to registers
RACL, RACU, and RACH before triggering RFTRG. Flag
RFC (2Ah.r5)
will change from 0 to
1 when all RAM locations have been filled. After RAM Filling has completed, the
microprocessor should clear RFTRG to 0.
Bit 5:
RFC - RAM Fill Completion Flag (read only)
This flag will change from 0 to 1 when all RAM locations have been filled with the value in
register
RAMWR (1Eh,w)
. This flag is clear when RFTRG is disabled.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| W88631F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
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