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參數(shù)資料
| 型號(hào)： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁(yè)數(shù)： | 29/102頁(yè) |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 25 - Revision 0.61
MBTC0 - Multi-Block Transfer Control 0 - (read/write 12h)
The host interface supports multi-block transfer without microprocessor intervention by following
sequence:
MBC (12h.4-0)
←
the number of block to be transferred minus 1 (ex. 3)
TWCH/L (03h/-2h)
←
the number of words to be transferred in each block minus 1 (ex.
1175)
TACH/L (05h/04h)
←
the starting point of the block (ex. F4h, FFh)
TBH/L (25h/24h)
←
the RAM block number of the first block to be transferred (ex. 5)
ATBHI/LO (35h/34h)
←
the total bytes to be transferred (ex. 9408)
ADTT (17h.w4)
←
1
PS:
STWCEN (18h.3)
should not be set in multi-block transfer operation.
When
ADTT
is set, host will receive HIRQ, check status, and then start to read data.
After the last word of one block (except the last one) is read by the host, the following hardware
sequence is executed:
TWCH/L (03h/02h)
←
reload
TACH/L (05h/04h)
←
reload
TBH/L (25h/24h)
←
auto-increment
MBC0 (12h.4-0)
←
auto-decrement
Flag
TENDb (01h.r6)
only becomes active at the end of data transfer of the last block. This register is
0 after chip reset, host reset and firmware reset.
3
2
1
0
N
N+1
N+2
N+3
5
6
7
8
MBC(12h.4-0)
TBH/L(25h/24)
data transfer
TENDb(01h.r6)
HIRQ
transfer trigger
status complete
TWC/TAC
reload
TWC/TAC
reload
TWC/TAC
reload
<Multi-Block Transfer Flow Example>
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