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參數(shù)資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數(shù)： | 59/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 55 - Revision 0.61
TARCTL - Target Control Register - (write 80h)
This register is used to control the automatic target search and header comparison. Since these
control bits are not changed by closing decoder, there is no need to write it before every time the
decoder is enabled.
Bit 7: TARGEN - Target Function Enable
Setting this bit high enables target search function but does not enable decoder
simultaneously. The operation of target search is triggered by setting
DECEN (0Ah.w7)
high.
Then the decoder generates first interrupt after the target sector, specified by
TARGET (84h-
86h)
, is found.
Bit 6: DSCEN - Decoding Sector Counting Enable
If
DSCEN (80h.6)
is enabled, flag
DSFULI (80h.r4)
becomes high if
DSCL (81h,r)
is equal to
DSTL (81h,w)
at the end of EDC-checking.
Bit 5: QEN - Q-channel extraction enable
Setting this bit high enables Q-channel extraction logic. This pin should be set high only
when
SCEN (2Ch.w6)
is high. Once decoder and Q-channel extraction are both enabled, the
extracted Q-channel bytes are written into the DRAM starting from offset 9E0h of each block
regardless of what mode of data is set.
Bit 4: QMSF - Q-channel MSF auto-load enable
If Q-channel extraction logic is enabled, setting this bit high enables the MSF bytes of Q-
channel to be automatically loaded to
HEAD0-2 (04h-06h,r)
.
Bit 3: ASTOPB - Automatic Decoder Stop on Error
If this bit is low, decoder would automatically stop on the following conditions:
HCEI (80h.r0)
activates if
HCEEN (80h.w0)
is enabled.
TNFI (80h.r1)
activates if
TNFEN (80h.w1)
is enabled.
LTTI (80h.r2)
activates if
LTTEN (80h.w2)
is enabled.
LASTBK (80h.r3)
activates if
BLIMEN (9Ah.5)
is enabled
DSFULI (80h.r4)
activates if
DSCEN (80h.w6)
is enabled.
STAERR (80h.r6)
activates if any Status Mask Bit is enabled
If this bit is low, the consistency of f/w and h/w should be carefully maintained. If this bit is
high, the decoder is controlled by microprocessor. This bit is default low after chip reset.
Bit 2: LTTEN - Larger Than Target Interrupt Enable
Setting this bit high enables
LTTI (80h.r2)
to be reflected on
SRIb (01h.r5)
.
Bit 1: TNFEN - Target Not Found Interrupt Enable
Setting this bit high enables
TNFI (80h.r1)
to be reflected on
SRIb (01h.r5)
.
Bit 0: HCEEN - Header Compare Error Interrupt Enable
Setting this bit high enables
HCEI(80h.r0)
to be reflected on
SRIb (01h.r5)
.
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