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參數(shù)資料
型號: W88113C
廠商: WINBOND ELECTRONICS CORP
英文描述: ATAPI CD-ROM DECODER & CONTROLLER
中文描述: ATAPI的CD - ROM解碼器
文件頁數(shù): 83/102頁
文件大小: 573K
代理商: W88113C
W88113C
Publication Release Date: Mar. 1999
- 79 - Revision 0.61
set TWCH/L (03h/02h) as 008Fh
set TACH/L (05h/04h) as 0800h
Case 3: The 2352 bytes of sync, header, user data and EDC&ECC are request by host.
set TBH/L (25h/24h) as 001Fh
set TWCH/L (03h/02h) as 0497h
set TACH/L (05h/04h) as FFF0h
If the requested data is not stored continuously in DRAM, e.g.
,
header and EDC&ECC data, more than one
transfer has to be triggered.
5.1.4 16-bit DRAM
High DRAM bandwidth is the key issue to support high disk speed and can be dramatically by using
16-bit DRAM.
The following setting should be made at initialization to utilize 16-bit DRAM.
The control bit
ALE2 (5Ch.3)
should be set high (default after chip reset).
The value of
RTC2-0 (2Ah.2-0,w)
should be
101
b (9 col) or
100
b (8 col).
The
Ring Control Registers (50h-57h)
should also be set to fully utilize the DRAM space.
Since DRAM access is based on linear addressing, there is no need of further firmware change.
5.1.5 EDO DRAM
EDO DRAM is designed to improve the DRAM read performance. The EDO DRAM support is
enabled by setting control bit
EDOEN (88h.w0)
high. When this bit is set high, the data latch timing
of DRAM changes to falling edge instead of rising edge of internal clock.
The timing of DRAM is controlled by
MRCD (88h.w5)
and
FRCDb (88h.w1)
. The slower timing may
be required to support some slower DRAMs.
MRCD
FRCDB
tRCD
tRP
tPC
Minimum Cycle
0
0
1 T
1.5 T
1 T
3 T
0
1
2 T
1.5 T
1 T
4 T
1
0
1.5 T
1 T
1 T
3 T
1
1
x
x
x
x
Note:
T
is the system clock period.
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