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參數(shù)資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數(shù)： | 41/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 37 - Revision 0.61
SCIACK - Subcode Interrupt Acknowledge - (write 22h)
Writing any value to this register de-activates
SCIb (01h.r0)
if
SCIEN (2CH.w4)
is enabled.
SUBSTA - Subcode Status Register - (read 22h)
When
SCIb (01h.r0)
is activated, the microprocessor can read this register to determine the reason of
interrupt.
Bits 7-5: Reserved
Bit 4:
QCRCOK
- Q-channel CRC OK flag
If Q-channel extraction is enabled, this bit reflects the status of CRC checking of Q-channel
information.
Bit 3: reserved
Bit 2:
MSS - Missing Subcode Sync
A missing-subcode-sync sets MSS high and negates
SCIb (01h.r0).
A microprocessor
interrupt is activated also if
SCIEN (2Ch.w4)
is enabled.
Bit 1:
NESBK - Normal End of Subcode Block
A normal-subcode-block-end sets NESBK high and negates
SCIb (01h.r0)
. A microprocessor
interrupt is activated also if
SCIEN (2Ch.w4)
is enabled.
Bit 0:
ISS - Illegal Subcode Sync
An illegal-subcode-sync sets ISS high and negates
SCIb (01h.r0)
. A microprocessor interrupt
is activated also if
SCIEN (2Ch.w4)
is enabled.
TBH/L - Transfer Block Register - (read/write 25h/24h)
If
LATXF (03h.7)
is low,
TBH/L
form a 9-bit counter that is used to specify the first RAM block to be
transferred, while registers
TACH/L (05h/04h,w)
specify the starting address relative to the beginning
of this RAM block. The block-offset transfer is carried within a
transfer ring
that is controlled by
DTRCH/L (53h/52h)
and
DTRBH/L (51h/50h)
. The buffer ring and transfer ring are usually defined in
the same range.
Note that
TBH/L (25h/24h)
do not increment automatically at the end of each transfer unless:
ACMEN (9CH.6)
is high
DINB (1Fh.1)
is low (data-in transfer is enabled)
LATXF (03h.7)
is low (block-offset transfer is used)
If
ACMEN (9Ch.6)
is high,
TCC (9Dh)
minus
N
and
TBH/L (25h/24h)
plus
N
right after
SKIPC (9Eh)
is
set
N
.
If
BICEN (9Ah.7)
is high and
BCFSEL (9Ah.5)
is low, the DSP buffering stop when buffering block
(internal) reach
TBK (9Bh,w)
.
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