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參數資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數： | 62/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 58 - Revision 0.61
TARGET0 - Target Minute Register - (read/write 84h)
TARGET1 - Target Second Register - (read/write 85h)
TARGET2 - Target Frame Register - (read/write 86h)
DACTL - Digital Audio Control Register - (read/write 87h)
This register is 00h after chip reset and host reset.
Bit 7: DA0EN - Digital Output 0 Enable
If this bit is high, the digital audio data output through
pin URS/DA0 (32)
.
Bit 6: CTLSEL - Control Bit Source Select
If this bit is high, the 4 control bits of Q channel are defined by
QCTL3-0 (87h,3-0)
.
Otherwise, these 4 control bits are extracted from external RAM. This bit is normal set low if
the Q-channel extraction work properly.
Bit 5-4: ACCU[1:0] - Clock Accuracy
These two bits are used as clock accuracy bits in digital audio output. These two bits are
usually set 00b.
Bit 3:0: QCTL[3:0] - Control Bits for Q Channel
If
CTLSEL (87h.6)
is high, these four bits are used as Q channel control bits in digital audio
output.
FEACTL - Feature Control Register - (read/write 88h)
This register is 00h after chip reset and host reset.
Bit 7:
LECAS - Latch Data with External CAS Signal
If this bit is high, input DRAM data is latched by external CASH/L signal instead of rising edge
of internal clock. This function can eliminate the timing difference between DRAM data and
its latch signal caused by various internal chip delays, depending on circumstances. This
function should not be used if
EDOEN (88h.1)
is high.
Bit 6:
LREF - Long Refresh Cycle
If this bit is high, the tRAS is 2.5 clocks instead 1.5 clocks for refresh cycle.
Bit 5: MRCD - Medium RAS to CAS Delay
The bit controls the timing of tRCD and tRP. If this bit is high the tRAS for RAS-only refresh
is 2 clocks and CAS-Before-RAS is not affected (1.5 clocks).
Bit 4:
SDBS - Subcode and DSP Block Synchronization
This bit provides block synchronization of CD-DA format data. If this bit is high, the buffering
of incoming serial data and subcode to the external RAM will synchronize to the same block
defined by
DDBH/L (29h/28h)
.
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|---|---|
| W88113CD | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | ATAPI CD-ROM DECODER & CONTROLLER |
| W88227F | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W88113CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88611P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
| W88631F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
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