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參數(shù)資料
型號: W6692
廠商: WINBOND ELECTRONICS CORP
元件分類: 通信及網(wǎng)絡
英文描述: PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器)
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: 14 X 20 MM, 2.75 MM HEIGHT, QFP-100
文件頁數(shù): 15/84頁
文件大小: 473K
代理商: W6692
W6692
Publication Release Date: October 1998
- 15 -
Revision A1
Figure 7.3 External transmitter circuitry
Figure 7.4 External receiver circuitry
After hardware reset, the receiver may enter power down state to save power. In thist state, the
internal clocks are turned off, but the analog level detector is still active to detect signal coming from
the S interface. The power down state is left either by non-INFO 0 signal from S interface or C/I
command from micro-processor.
7.2.2 Receiver Clock Recovery And Timing Generation
A Digital Phase Locked Loop (DPLL) circuit is used to derive the receive clock from the received data
stream. This DPLL uses a 7.68 MHz clock as reference. According to I.430, the transmit clock is
normally delayed by 2 bit time from the receive clock. The "total phase deviation input to output" is -
7% to +15% of a bit period. In some cases, delay compensation may be needed to meet this
requirement (see OPS1-0 bits in D_CTL register).
SX1
SX2
18-33
18-33
GND
ο
V
DD
2:1
100
SR1
SR2
1.8 K
1.8 K
GND
ο
V
DD
8.2 K
8.2 K
2:1
100
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