
W6692
Publication Release Date: October 1998
- 3 -
Revision A1
8.1.25 S/Q Channel Receive Register SQR Read Address 60H..............................................................55
8.1.26 S/Q Channel Transmit Register SQX Write Address 64H.............................................................56
8.1.27 Peripheral Control Register PCTL Read/Write Address 68H.........................................................56
8.1.28 Monitor Receive Channel MOR Read Address 6CH.....................................................................57
8.1.29 Monitor Transmit Channel MOX Read/Write Address 70H...........................................................58
8.1.30 Monitor Channel Status Register MOSR Read_clear Address 74H.........................................58
8.1.31 Monitor Channel Control Register MOCR Read/Write Address 78H.................................58
8.1.32 GCI Mode Control Register GCR Read/Write Address 7CH................................................59
8.1.33 Peripheral Address Register XADDR Read/Write Address F4H....................................................60
8.1.34 Peripheral Data Register XDATA Read/Write Address F8H...................................................61
8.1.35 Serial EEPROM Control Register EPCTL Write Address 68H .......................................................62
8.2 B1 HDLC controler ...............................................................................................................................62
8.2.1 B1_ch receive FIFO B1_RFIFO Read Address 80H........................................................................63
8.2.2 B1_ch transmit FIFO B1_XFIFO Write Address 84H ....................................................................63
8.2.3 B1_ch command register B1_CMDR Write Address 88H...............................................................63
8.2.4 B1_ch Mode Register B1_MODE Read/Write Address 8CH............................................................64
8.2.5 B1_ch Extended Interrupt Register B1_EXIR Read_clear Address 90H............................................66
8.2.6 B1_ch Extended Interrupt Mask Register B1_EXIM Read/Write Address 94H ..................66
8.2.7 B1_ch Status Register B1_STAR Read Address 98H...............................................................66
8.2.8 B1_ch Address Mask Register 1 B1_ADM1 Read/Write Address 9CH.............................................67
8.2.9 B1_ch Address Mask Register 2 B1_ADM2 Read/Write Address A0H.............................................67
8.2.10 B1_ch Address Register 1 B1_ADR1 Read/Write Address A4H .............................................68
8.2.11 B1_ch Address Register 2 B1_ADR2 Read/Write Address A8H ....................................................68
8.2.12 B1_ch Receive Frame Byte Count Low B1_RBCL Read Address ACH...........................................68
8.2.13 B1_ch Receive Frame Byte Count High B1_RBCH Read Address B0H..........................................68
8.3 B2 HDLC controller...............................................................................................................................69
8.4 PCI Configuration Register...................................................................................................................70
8.4.1 Device/Vendor ID Register Read Address 00
H
...............................................................................71
8.4.2 Status/Command Register Read/Write Address 04
H
......................................................................71
8.4.3 Class Code/Revision ID Register Read Address 08
H
....................................................................73
8.4.4 Header Type/Latency Timer Register Read Address 0C
H
..............................................................74
8.4.5 Base Address Register 0 Read/Write Address 10
H
.......................................................................74
8.4.6 Base Address Register 1 Read/Write Address 14
H
.........................................................................76
8.4.7 Subsystem/Subsystem Vendor ID Register Read Address 2C
H
.......................................................76
8.4.8 Interrupt Line Register Read/Write Address 3C
H
..........................................................................77