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參數(shù)資料
型號(hào)： W6692
廠商： WINBOND ELECTRONICS CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器)
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.75 MM HEIGHT, QFP-100
文件頁(yè)數(shù)： 18/84頁(yè)
文件大小： 473K
代理商： W6692
W6692
- 18 -
Table 7.2 Layer 1 command codes
COMMAND
SYM.
ECK
RST
SCP
SSP
AR8
AR10
EAL
DRC
CODE
0000
0001
0100
0010
1000
1001
1010
1111
DESCRIPTION
Enable clock
Layer 1 reset
Send continuous pulses
Send single pulses
Activate request at priority 8
Activate request at priority 10
Enable analog loopback
Deactivate layer 1
Enable internal clocks
Layer 1 reset
Send continuous pulses at 96 KHz
Send isolated pulses at 2 KHz
Activate layer 1 and set D channel priority level to 8
Activate layer 1 and set D channel priority to 10
Enable analog loopback
Deactivate layer 1 and disable internal clocks
Table 7.3 Layer 1 indication codes
INDICATION
SYM.
CE
DRD
CODE
0111
0000
DESCRIPTIONS
Clock Enabled
Deactivate request
downstream
Level detected
Activate request downstream
Test indication
Internal clocks are enabled
Deactivation request by S interface, i.e INFO 0
received
Signal received, receiver not synchronous
INFO 2 received
Analog loopback activated or continuous zeros or
single zeros transmitted
Level detected during test function
INFO 4 received, D channel priority is 8 or 9
LD
ARD
TI
0100
1000
1010
Awake test indication
Activate indication with
priority class 1
Activate indication with
priority class 2
Clock disabled
ATI
AI8
1011
1100
AI10
1101
INFO 4 received, D channel priority is 10 or 11
CD
1111
Layer 1 deactivated, internal clocks are disabled
7.2.3.2 State Transition Diagrams
The followings are the state transition diagrams which implement the activation/deactivation state
matrix in I.430 (TABLE 5/I.430). The "command" and "s receive" entries in each state octagon keeps
the state, the "indication" and "s transmit" entries in each state octagon are the state outputs. For
example, at "F3 Deactivated with clock" state, the layer 1 will stay at this state if the command is
"ECK" and the INFO 0 is received on S interface. At this state, it provides "CE" indication to the
micro-processor and transmits INFO 0 on S interface. A "AR8/10" command causes transition to F4
and non-INFO 0 signal causes transition to F5. Note that the command code writtern by the micro-
processor in CIX register and indication code written by layer 1 in CIR register are transmitted
repeatedly until a new code is written.
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W6692A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT
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W6694 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller
W6694A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface
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