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參數資料
| 型號： | W6692 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 31/84頁 |
| 文件大小： | 473K |
| 代理商： | W6692 |
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W6692
Publication Release Date: October 1998
- 31 -
Revision A1
The data between the opening flag and the CRC field are stored in D_RFIFO. For LAPD frame, this
includes the address field, control field and information field.
When a D_RMR or D_RME interrupt is generated, the micro-processor must read out the data from
D_RFIFO and issues the Receive Message Acknowledgement command (D_CMDR: RACK bit) to
explicitly acknowledge the interrupt. The micro-processor must handle the interrupt before more than
64 bytes of data are received. This corresponds to a maximum micro-processor reaction time of 32
mS at 16 kbps data rate.
If the micro-processor is late in handling the interrupt, the incoming additional bytes will result in a
"data overflow" interrupt and status bit.
7.6.3 Transmission of Frames in D Channel
A 128-byte FIFO is provided in the transmit direction. If the transmit FIFO is ready (which is indicated
by a D_XFR interrupt ), the micro-processor can write up to 64 bytes of data into the FIFO and use
the XMS command bit to start frame transmission. The HDLC transmitter sends the opening flag first
and then sends the data in the transmit FIFO.
The micro-processor must write the address, control and information field of a frame into the transmit
FIFO.
Every time no more than 64 bytes of data are left in the transmit FIFO, the transmitter generates a
D_XFR interrupt to request another block of data. The micro-processor can then write further data to
the transmit FIFO and enables the subsequent transmission by issuing an XMS command.
If the data written to the FIFO is the last segment of a frame, the micro-processor issues the XME
(Transmit Message End) and XMS command bits to finish the frame transmission. The transmitter
then transmits the data in the FIFO and appends CRC and closing flag.
If the micro-processor fails to respond the D_XFR interrupt within a given time (32 mS), a data
underrun condition will occur. The W6692 will automatically reset the transmitter and send inter frame
time fill pattern (all 1's) on D channel. The micro-processor is informed about this condition via an
XDUN (Transmit Data Underrun) interrupt in D_EXIR register. The microprocessor must wait until
transmit FIFO ready (via XFR interrupt ), re-write data, and issue XMS command to re-transmit the
data.
It is possible to abort a frame by issuing a D_CMDR: XRST (D channel Transmitter Reset) command.
The XRST command resets the transmitter and causes a transmit FIFO ready condition.
After the micro-processor has issued the XME command, the successful termination of transmission
is indicated by an D_XFR interrupt.
The inter-frame time fill pattern must be all 1's, according to ITU-T I.430.
Collisions which occur on the D channel of S interface will cause an D_EXIR: XCOL interrupt. A
XRST (Transmitter Reset) command must be issued and software must wait until transmit FIFO ready
(via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
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| W6694 | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| W6810 | SINGLE-CHANNEL VOICEBAND CODEC |
| W6810IE | SINGLE-CHANNEL VOICEBAND CODEC |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W6692A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
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