
W6692
Publication Release Date: October 1998
- 41 -
Revision A1
7.10 Peripheral Control
In PCI card with POTS application, the peripheral devices such as CODEC, DTMF and SLIC can be
directly controlled by W6692, therefore preclude the need for another PCI controller chip. The
peripheral control function includes timer, interrupt inputs and programmable IOs or microprocessor
interface.
There are two timers implemented in W6692: D_TIMR and TIMR2. D_TIMR is a long period timer
whcich can be used to control the 1 sec, 2 sec ON/OFF of ring tone. While TIMR2 is a short period
timer which can be used to generate the tens hertz of ring signal.
ADDRESS
INTERRUPT
STATUS
INTERRUPT
MASK
OUTPUT
PIN
PERIOD
CYCLIC
D_TIMR
10H
DEXIR: TEXP
DEXIM: TEXP
No
(0..6) x 2.048 s
+(1..32) x 64
mS
Yes
(CNT = 7)
TIMR2
4CH
DEXIR: TIN2
DEXIM: TIN2
TOUT2
(1..63) mS
Yes
(TMD = 1)
TOUT2 toggles when TIMR2 counts down to zero. For example, if the timer period is 1 mS, then the
period of TOUT2 is 2 mS.
There are two interrupt input pins: XINTIN0, XINTIN1. Whenever signal level changes (eith rising or
falling), a maskable interrupt is generated which in turn will make an interrupt request on PCI bus if it
is unmasked. The interrupt status bits are ISTA: XINT0, ISTA: XINT1. The mask bits are IMASK:
XINT0, IMASK: XINT1. In addition, the signal level can be read at bits SQR: XIND0, SQR; XIND1.
These pins can be used for monitor of SLIC hook state and/or DTMF data valid status.
The IO interface can be programmed as simple IO (PCTL: XMODE = 0) or 8-bit microprocessor
interface (PCTL: XMODE = 1). As simple IOs, the directions of the 11 pins are selected via OE5-0
bits in PCTL register and the read/write data accessed via XADDR and XDATA registers. As output,
the register data is output on the pin, as input, the current level of pin is read in. In this mode, a
maximum of 11 IO ports are supported.
If programmed as 8-bit microprocessor mode, an 8-bit multiplexed bus is used to control peripheral
deveces. The address and data are multiplexed on XAD7-0. XALE is used for address latch and
XRDB, XWRB are used for read/write strobe. To access peripheral device, first write the desired
address in XADDR register and then read/write data at XDATA register. In this mode, a maximum of
256 byte ports can be supported by adding some glue TTLs on board.