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參數資料
| 型號： | W6692 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 16/84頁 |
| 文件大小： | 473K |
| 代理商： | W6692 |
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W6692
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Table 7.1 Output phase delay compensation table
OPS1
OPS0
EFFECT
0
0
No phase delay compensation
0
1
Phase delay compensation 260 nS
1
0
Phase delay compensation 520 nS
1
1
Phase delay compensation 1040 nS
W6692 does not need RC filter on receiver side, therefore zero delay compensation is selected
normally. This is the default setting.
The PCM output clocks (PFCK1-2, PBCK) are synchronous to the S-interface timing.
7.2.3 Layer 1 Activation/Deactivation
The layer 1 activation/deactivation procedures are implemented by a finite state machine. The state
transitions are triggered by signals received at S interface or commands issued from micro-processor.
The state outputs signals to S interface and indication to micro-processor. The CIX register is used by
micro-processor to issue command, and the CIR register is used by micro-processor to receive
indication.
Some commands are used for special purposes. They are "layer 1 reset", "analog loopback", "send
continuous zeros" and "send single zero".
7.2.3.1 States Descriptions and Command/Indication Codes
F3 Deactivated without clock
This is the "deactivated" state of ITU-T I.430. The receive line awake unit is active except during a
hardware reset pulse. After reset, once the indication "1111" has been read out, internal clocks will
turn off and stay at this state if INFO 0 is received on the S line. The turn off time is approximate 93
mS. The command ECK must be issued to activate the clocks.
F3 Deactivated with clock
This state is identical to "F3 Deactivated without clock" except the internal clocks are enabled. The
state is entered by a ECK command. The clocks are enabled approximately 0.5 mS to 4 mS after the
ECK command, depending on the crystal capacitances. (It is about 0.5 mS for 12 to 33 pF
capacitance).
F3 Awaiting Deactivation
The W6692 enters this state after receiving INFO 0 (in states F5 to F8) for 16 mS (64 frames). This
time constant prevents spurious effect on S interface. Any non-INFO 0 signal on the S interface
causes transition to "F5 Identifying Input" state. If this transition does not occur in a specific time
(500
1000 mS), the micro-processor may issue DRC or ECK command to deactivate layer 1.
F4 Awaiting Signal
This state is reached when an activate request command has been received. In this state, the layer 1
transmits INFO1 and INFO 0 is received from the S interface. The software starts timer T3 of I.430
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W6692A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
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