
W6692
- 50 -
8.1.11 D_ch Receive Status Register D_RSTA
Read
Address 28H
Value after reset: 20H
7
6
5
4
3
2
1
0
RDOV
CRCE
RMB
RDOV Receive Data Overflow
A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive
FIFO. The data overflow condition will set both the status and interrupt bits. It is recommended that
software must read the RDOV bit after reading data from D_RFIFO at RMR or RME interrupt. The
software must abort the data and issue a RRST command to reset the receiver if RDOV = 1. The
frame overflow condition will not set this bit.
CRCE CRC Error
This bit indicates the result of frame CRC check:
0: CRC correct
1: CRC error
RMB Receive Message Aborted
A "1" means that a sequence of seven 1's was received and the frame is aborted. Software must
issue RRST command to reset the receiver.
Note: Normally D_RSTA register should be read by the micro-processor after a D_RME interrupt. The contents of D_RSTA are
valid only after a D_RME interrupt and remain valid until the frame is acknowledged via a RACK bit.
8.1.12 D_ch SAPI Address Mask
D_SAMRead/Write
Address 2CH
Value after reset: 00H
7
6
5
4
3
2
1
0
SAM7
SAM6
SAM5
SAM4
SAM3
SAM2
SAM1
SAM0
This register masks(disables) the first byte address comparison of the incoming frame. If the mask bit
is "1" the corresponding bit comparisons with D_SAP1, D_SAP2 are disabled. Comparison with
SAPG is always performed.
Note: For the LAPD frame, the least significant two bits are the C/R bit and EA = 0 bit. It is suggested that the comparison with
C/R bit be masked. EA = 0 for two octet address frame e.g LAPD, EA = 1 for one octet address frame.
8.1.13 D_ch SAPI1 Register
D_SAP1
Read/Write
Address 30H
Value after reset: 00H
7
6
5
4
3
2
1
0
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
This register contains the first choice of the first byte address of received frame. For LAPD frame,
SA17 - SA12 is the SAPI value, SA11 is C/R bit and SA10 is zero.