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參數資料
型號: W6692
廠商: WINBOND ELECTRONICS CORP
元件分類: 通信及網絡
英文描述: PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器)
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: 14 X 20 MM, 2.75 MM HEIGHT, QFP-100
文件頁數: 65/84頁
文件大小: 473K
代理商: W6692
W6692
Publication Release Date: October 1998
- 65 -
Revision A1
ITF Inter-frame Time Fill
Defines the inter-frame time fill pattern in transparent mode.
0: Mark. The binary value "1" is transmitted.
1: Flag. This is a sequence of "01111110".
EPCM Enable PCM Transmit/Receive
0: Disable data transmit/ receive to/from PCM port. The frame synchronization clock PFCK1 is
held LOW.
1: Enable data transmit/ receive to/from PCM port. The frame synchronization clock PFCK1 is
active.
BSW1-0 B Channel Switching Select
These two bits determine the connection in B1 channel:
BSW1
0
0
1
1
BSW0
0
1
0
1
CONNECTION
layer 1
HDLC
layer 1
PCM
HDLC
PCM
layer 1
PCM, PCM
HDLC
Note: The connection with micro-controller is through HDLC controller. When HDLC connects with layer 1, either transparent or
extended transparent mode can be used. When HDLC connects with PCM port, only extended transparent mode can be
used and the EPCM bit must be set to enable PCM function.
SW56 Switch 56 Traffic
0: The data rate in B1 channel is 64 kbps.
1: The data rate in B1 channel is 56 kbps. The most significant bit in each octet is fixed at "1".
Note: In 56 kbps mode, only transparent mode can be used.
FTS1-0 FIFO Threshold Select
These two bits determine the B1 channel receive and transmit FIFO's threshold setting. An interrupt is
generated when the number of received data or the number of vacancies in XFIFO reaches the
threshold value.
FTS1
FTS0
THRESHOLD (BYTE)
0
0
64
0
1
Reserved
1
0
96
1
1
Not allowed
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