- 您現在的位置：買賣IC網 > PDF目錄363893 > W6692 (WINBOND ELECTRONICS CORP) PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) PDF資料下載
參數資料
| 型號： | W6692 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 44/84頁 |
| 文件大小： | 473K |
| 代理商： | W6692 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
W6692
- 44 -
8.1.1 D_ch receive FIFO
D_RFIFO
Read
Address 00H
The D_RFIFO has a length of 128 bytes.
After a D_RMR interrupt, exactly 64 bytes are available.
After a D_RME interrupt, the number of bytes available equals RBC5-0 bits in the D_RBCL register.
8.1.2 D_ch transmit FIFO
D_XFIFO
Write
Address 04H
The D_XFIFO has a length of 128 bytes.
After an D_XFR interrupt, up to 64 bytes of data can be written into this FIFO for transmission. At the
first time, up to 128 bytes of data can be written.
8.1.3 D_ch command register D_CMDR
Write
Address 08H
Value after reset: 00H
7
6
5
4
3
2
1
0
RACK
RRST
STT
XMS
XME
XRST
RACK Receive Acknowledge
After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets
this bit to acknowledge the interrupt.
RRST Receiver Reset
Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data.
STT Start Timer
The D_ch hardware timer is started when this bit is set to one. The timer is stopped when it expires or
by a write of the D_TIMR register. Note that the timer must be in external mode.
XMS Transmit Message Start/Continue
Setting this bit will start or continue the transmission of a frame. The opening flag is automatically
added by the HDLC controller.
XME Transmit Message End
Setting this bit indicates the end of frame transmission. The D_ch HDLC controller automatically
appends the CRC and the closing flag after the data transmission.
Note: If the frame
≤
64 bytes, XME plus XMS commands must be issued at the same time.
XRST Transmitter Reset
Setting this bit resets the D_ch HDLC transmitter and clears the D_XFIFO. The transmitter will send
inter frame time fill pattern (which is 1's) immediately. This command also results in a transmit FIFO
ready condition.
相關PDF資料 |
PDF描述 |
|---|---|
| W6693A | USB Bus ISDN S/T Interface Controller(USB總線的ISDN S/T接口控制器) |
| W6694 | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| W6810 | SINGLE-CHANNEL VOICEBAND CODEC |
| W6810IE | SINGLE-CHANNEL VOICEBAND CODEC |
| W6810IR | SINGLE-CHANNEL VOICEBAND CODEC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W6692A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
發布緊急采購，3分鐘左右您將得到回復。