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參數資料
| 型號： | W6692 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 64/84頁 |
| 文件大小： | 473K |
| 代理商： | W6692 |
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W6692
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RACK Receive Message Acknowledge
After a RMR or RME interrupt, the micro-processor reads out the data in B1_RFIFO, it then sets this
bit to explicitly acknowledge the interrupt.
RRST Receiver Reset
Setting this bit resets the B1_ch HDLC receiver.
RACT Receiver Active
The B1_ch HDLC receiver is active when this bit is set to "1". This bit is write only. The receiver must
be in active state in order to receive data.
XMS Transmit Message Start/Continue
In transparent mode, setting this bit initiates the transparent transmission of B1_XFIFO data. The
opening flag is automatically added to the message by the B1_ch HDLC controller. Zero bit insertion
is performed on the data. This bit is also used in subsequent transmission of the frame.
In extended transparent mode, settint this bit activates the transmission of B1_XFIFO data. No flag,
CRC or zero bit insertion is added on the data.
XME Transmit Message End
In transparent mode, setting this bit indicates the end of the whole frame transmission. The B1_ch
HDLC controller transmits the data in FIFO and automatically appends the CRC and the closing flag
sequence in transparent mode.
In extended transparent mode, setting this bit stops the B1_XFIFO data transmission.
XRST Transmitter Reset
Setting this bit resets the B1_ch HDLC transmitter and clears the B1_XFIFO. The transmitter will send
inter frame time fill pattern on B channel. This command also results in a transmit FIFO ready
condition.
8.2.4 B1_ch Mode Register
B1_MODE
Read/Write
Address 8CH
Value after reset: 00H
7
6
5
4
3
2
1
0
MMS
ITF
EPCM
BSW1
BSW0
SW56
FTS1
FTS0
MMS Message Mode Setting
Determines the message transfer modes of the B1_ch HDLC controller:
0: Transparent mode. In receive direction, address comparison is performed on each frame. The
frames with matched address are stored in B1_RFIFO. Flag deletion, CRC check and zero bit
deletion are performed. In transmit direction, the data is transmitted with flag insertion, zero bit
insertion and CRC generation.
1: Extended transparent mode. In receive direction, all data are received and stored in the
B1_RFIFO. In transmit direction, all data in the B1_XFIFO are transmitted without alteration.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W6692A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
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