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參數資料
| 型號： | W6692 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 45/84頁 |
| 文件大小： | 473K |
| 代理商： | W6692 |
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W6692
Publication Release Date: October 1998
- 45 -
Revision A1
8.1.4 D_ch Mode Register
D_MODE
Read/Write
Address 0CH
Value after reset: 00H
7
6
5
4
3
2
1
0
MMS
RACT
TMS
TEE
MFD
DLP
RLP
MMS Message Mode Setting
Determines the message transfer mode of the D_ch HDLC controller:
MMS
MODE
ADDRESS
BYTES
FIRST BYTE ADDRESS
COMPARISON WITH:
SECOND BYTE ADDRESS
COMPARISON WITH:
0
Transparent mode
2
D_SAP1, D_SAP2, SAPG
D_TEI1, D_TEI2, TEIG
Notes:
1. D_SAP1, D_SAP2: two programmable address values for the first received address byte; SAPG = fixed value
FC/FEH. D_TEI1, D_TEI2 : two programmable address values for the second received address byte; TEIG = fixed
value FFH.
2: The first byte address comparison can be masked by D_SAM register, and the second byte address comparison can
be masked by D_TAM register. But the comparisons with SAPG and TEIG cannot be disabled.
RACT Receiver Active
Setting this bit activates the D_ch HDLC receiver. This bit can be read. The receiver must be in
active state in order to receive data.
TMS Timer Mode Setting
Sets the operating mode of the D_ch timer. In the external mode (TMS = 0), the timer is controlled by
the processor. It is started by setting the STT bit in D_CMDR and is stopped by a write of the D_TIMR
register or when it expires. When the timer expires, a maskable D_EXP interrupt is generated.
In the internal mode (TMS = 1), the timer is used for internal test purposes. It should not be selected
for normal chip operation.
TEE Terminal Equipment Function Enable
The terminal equipment function is enabled when this bit is "1". The supported functions are:
- Watchdog timer, enabled when TEE = 1 and D_CTL: TPS =1
- Exchange awake, enabled when TEE = 1 and D_CTL: TPS =0
When the watchdog timer has been enabled, the micro-processor has to program the WTT1, 2 bits in
a specified manner within 1024 mS to reset and restart the timer. Otherwise, the timer will expire in
1024 mS and a WEXP interrupt together with a 125
μ
S reset pulse on TRST pin is generated.
The exchange awake condition is initiated by C/I code change condition. A 16 mS reset pulse on
TRST pin is generated.
Switching TPS bit will reset the watchdog timer.
The TEE bit is cleared only by a hardware reset.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W6692A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
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