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參數(shù)資料
型號(hào)： W6692
廠商： WINBOND ELECTRONICS CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器)
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.75 MM HEIGHT, QFP-100
文件頁(yè)數(shù)： 32/84頁(yè)
文件大小： 473K
代理商： W6692
W6692
- 32 -
7.7 B Channel HDLC Controller
There are two B channel HDLC controllers. Each B channel HDLC controller provides two operation
modes:
- Transparent mode
characteristics:
* 2 byte address field
* Receive address comparison maskable bit-by-bit
* Data between opening flag and CRC (not included) stored in receive FIFO
* Flag generation/ deletion
* Frame Check Sequence generation/ check with CRC_ITU-T polynominal
* Zero bit insertion/ deletion
- Extended transparent mode
characteristics:
* All data transmitted/ received without modification
* No address comparison
* No flag generation/ detection
* No FCS generation/ check
* No bit stuffing
For PCM-HDLC connection, only extended transparent mode can be selected.
The data rate in B channel can be set at 64 kbps or 56 kbps by the B1_MODE (B2_MODE): SW56
bit.
7.7.1 Reception of Frames in B Channel
A 128-byte FIFO is provided in the receive direction. The receive FIFO threshold can be set at 64 or
96 bytes by the Bn_MODE register. If the number of received data reaches the threshold, a Receive
Message Ready (RMR) interrupt will be generated.
The operations for reception of frames differ in each mode:
Transparent mode
: The received frame address is compared with the contents in receive address
registers. In addition, the comparisons can be selectively masked bit-by-bit via address mask
registers. Comparison is disabled when the corresponding mask bit is "1".
In addition, flag recognition, CRC check and zero bit deletion are also performed. The result of CRC
check is indicated in Bn_STAR:CRCE bit. The data between opening flag and CRC field (not
included) is stored in receive FIFO. Two interrupts are used for the reception of data. The RMR
interrupt in Bn_EXIR register indicates at least a threshold block of data have been put in the receive
FIFO. The RME interrupt in Bn_EXIR register indicates the end of frame has been received. The
micro-processor can read out a threshold length of data from receive FIFO at RMR interrupt, or all
the data in receive FIFO at RME interrupt. At each RMR/ RME interrupt, micro-processor must issue
a Receive Message Acknowledgement(RACK) command to explicitly acknowledge the interrupt.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W6692A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT
W6692ACD 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC
W6692ACF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC
W6694 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller
W6694A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface
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