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參數資料
| 型號： | W6692 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 33/84頁 |
| 文件大小： | 473K |
| 代理商： | W6692 |
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W6692
Publication Release Date: October 1998
- 33 -
Revision A1
The micro-processor reaction time for RMR/ RME interrupt depends on the FIFO threshold setting
and B channel data rate. For example, it is 8 mS if the FIFO threshold is 64 and the B channel data
rate is 64 kbps.
If the micro-processor is late in handling the interrupt, the incoming additional bytes will result in a
"data overflow" interrupt and status bit.
Extended transparent mode: In this mode, all data received are stored in the receive FIFO without
any modification. Every time up to a threshold length of data has been stored in the FIFO, a Bn_RMR
interrupt is generated.
In this mode, there is no RME interrupt.
The micro-processor must react to the RMR interrupt in time, otherwise a "data overflow" interrupt
and status bit will be generated.
7.7.2 Transmission of Frames in B Channel
A 128-byte FIFO is provided in the transmit direction. The FIFO threshold can be set at 64 or 96
bytes. The transmitter and receiver use the same FIFO threshold setting.
The transmit operations differ in both modes:
Transparent mode
:
In this mode, the following functions are performed by the transmitter automatically:
- Flag generation
- CRC generation
- Zero bit insertion
The fields such as address, control and information are provided by the micro-processor and are
stored in transmit FIFO. To start the frame transmission, the micro-processor issues a XMS (Transmit
Message Start) command. The transmitter requests another block of data via XFR interrupt when
more than a threshold length of vacancies are left in the FIFO.The micro-processor then writes up to
a threshold length of data into the FIFO and activates the subsequent transmission of the frame by a
XMS command too. The micro-processor indicates the end of the frame transmission by issuing XME
(Transmit Message End) and XMS commands at the same time. The transmitter then transmits all the
data left in the transmit FIFO and appends the CRC and closing flag. After this, a XFR interrupt is
generated.
The inter-frame time fill pattern can be programmed to 1's or flags.
During the frame transmission, the micro-processor reaction time for the XFR interrupt depends on
the FIFO threshold setting and B channel data rate. For example, it is 8 mS if the FIFO threshold is
64 and the B channel data rate is 64 kbps. If the micro-processor fails to responds within the given
reaction time, the transmit FIFO will be underrun. In this case, the W6692 will automatically reset the
transmitter and send the inter frame time fill pattern on B channel. The micro-processor is informed
about this via a Transmit Data Underrun interrupt (XDUN bit in Bn_EXIR register). The
microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS
command to re-transmit the data.
The micro-processor can abort a frame transmission by issuing a Transmitter Reset command (XRES
bit in Bn_CMDR register). The XRES command resets the transmitter and sends inter frame time fill
pattern on B channel. It also results in a transmit pool ready condition.
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| W6694 | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| W6810 | SINGLE-CHANNEL VOICEBAND CODEC |
| W6810IE | SINGLE-CHANNEL VOICEBAND CODEC |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W6692A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
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