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參數(shù)資料
| 型號(hào)： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數(shù)： | 17/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-17-
Publication Release Date: 10/07/97
7.3 Timer / Counter
Timer/Counter megacell
Peripheral
Interface
TCR1
TICR1
TCR2
TICR2
TCLK
TINT1
TINT2
FIGURE 7.5 TIMER/COUNTER MEGACELL
Two 24-bit decrementing timers are implemented. When the timer's interrupt enable bit is set to one
and the counter decrements to zero, the timer will assert the associated interrupt signal. The interrupt signal
will assert one of the 32 external interrupts defined by the EI bits in the control register. When a timer reaches
zero, the timer hardware reloads the counter with the value from the timer initial count register and continues
decrementing.
Each timer is controlled and initialized by two registers: a timer control register and an timer initial
count register. These registers are all memory mapped I/O registers.
7.3.1 Timer Control register:
pre-scalar
0
31
TCR
IE
CE
TI
24
23
4
reserved
1 2 3
Pre-Scalar (PS)
: A pre-scalar value can be used to divide the input clock.
Interrupt Enable bit (IE)
: When IE is set to one and the counter decrements to zero, the timer
asserts its interrupt signal to interrupt the CPU.
Counter Enable bit (CE)
: Setting the CE bit to one causes the timer to begin decrementing.
Setting the CE bit to zero stops the timer.
Timer Interrupt bit (TI)
: The timer sets this bit to one to indicate that it has decrement to zero.
This bit remain one until software sets it to zero.
7.3.2 Timer Initial Count Register:
0
31
Timer Initial Count
TICR
7 8
reserved
A 24-bit read/write register for the initial counter value.
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