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參數資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數： | 27/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-27-
Publication Release Date: 10/07/97
1
0
N
1
1
X
1
2
B
1
3
C
1
4
V
Description
1
5
M
1
6
2
3
2
4
rv
2
5
G
2
6
F
2
7
R
2
8
Q
2
9
P
3
0
D
3
1
0
Y
Field
rv
Y
Z
E
1
Z
2 ... 4
rv
5
E
6
S
7
T
8
H
9
L
...
C/B
I
Reserved bits.
Data debug trap disable.
Instruction debug trap disable.
Little endian mode enable. When 1, all instruction fetches and loads/stores are little endian. The E bit after
RESET is set according to the state of ENDIAN pin.
Secure Interval Timer. When 1, the Interval Timer is readable only by code executing at the most privileged
level. When 0, the Interval Timer is readable by code executing at any privilege level.
Taken branch enable. When 1, any taken branch is terminated with a taken branch trap.
Higher-privilege transfer trap enable.
Lower-privilege transfer trap enable.
Nullify. The current instruction is nullified when this bit is 1.
Non-existent register bit.
Taken branch. The B-bit is set to 1 by any taken branch instruction and set to 0 otherwise.
Non-existent register bit.
Divide step correction. The integer primitive instruction records intermediate status in this bit to provide a
non-restoring divide primitive.
High-priority machine check mask. When 1, High Priority Machine Checks (HPMCs) are masked. Normally
0, this bit is set to 1 after HPMC and set to 0 after all other interruptions.
Carry/borrow bits. These bits are updated by some instructions from the corresponding carry/borrow
outputs of the 4-bit digit of the ALU.
Debug trap enable.
Non-existent register bit.
Recovery counter enable. When 1, recovery counter traps occur if bit 0 of the recovery counter is a 1. This
bit also enables decrementing of the recovery counter.
Interrupt state collection enable. When 1, interruption state is collected.
Non-existent register bit.
Non-existent register bit.
External interruption, power failure interrupt, and low-priority machine check interruption unmask. When 1,
these interruptions are unmasked and can cause an interruption.
FIGURE 8.2 PROCESSOR STATUS WORD
S
T
H
L
N
X
B
C
V
M
C/B
G
F
R
Q
P
D
I
8.1.4 Control registers
There are twenty-five control registers in W90100, numbered CR0, and CR8 through CR31, which
contain system state information. Figure 8.3 shows the control registers. The access of CR 11, 16, 26, and 27
are described in the following table (table 8.4). Those control registers not listed in table 8.4 are only accessible
by code executing at the most privileged level. Control registers 1 through 7 are reserved registers. The unused
bits of the Coprocessor Configuration Register are reserved bits. The unused bits of the Shift Amount Register
are nonexistent bits. In Level systems, CRs 8, 9, 12, 13, 17, and 20 are nonexistent registers.
0
31
CR 0
CR 1
Recovery Counter
reserved
reserved
Nonexistent registers
Nonexistent registers
CR 7
CR 8
CR 9
CR 10
CR 11
CR 12
CR 13
CR 14
reserved
SCR (8 bits)
CCR (8 bits)
SAR (5)
nonexistent
Nonexistent registers
Nonexistent registers
Interruption Vector Address
reserved
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