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參數資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數： | 34/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-34-
Publication Release Date: 10/07/97
8.3 DMA Controller (DMAC) Registers
Source Starting Address Register (SSAR0=200, SSAR1=210)
: SSAR is a read/write 32-bit register that contains
the starting address of the DMA transfer source.
Target Starting Address Register (TSAR0=204, TSAR1=214)
: TSAR is a read/write 32-bit register that contains the
starting address of the DMA transfer target.
Length/Count Register (LETH0=208, LETH1=218)
: LETH is a read/write 32-bit register that records the counts of
current DMA transfer.
DMA Channel Mode Register (MODE0=20C, MODE1=21C)
: The MODE register specifies the operation mode of
each channel.
The
Wait State Number
specifies the number of wait state needed for the particular DMA channel.
The
Recovery State Number
specifies the number of wait state needed for the recovery of the DMA
channel.
The
channel terminal count flags
indicate that a DMA operation has stopped.
The
DMA channel enable bits
enable or suspend a DMA operation after a channel is set up. If a
enable bit for a channel is cleared when a channel is active, the DMA will be suspended after pending
requests for the channel are serviced. The DMA operation will resume normally when the bit is reset.
NWait State
Recovery State
Terminal Count Flag
Transfer Start (only for memory-to-memory)
DMA Transfer Type
00: memory to memory
01: memory to I/O
10: I/O to memory
11: reserved
DMA is used by CODEC
MODE
Terminal Indicator
0: Polling
1: Interrupt
DMA is used by Parallel Port (ECP)
DMA Channel Enable Bit
TC_ENB, used for CODEC
Transfer Type: Block (0) or Demand(1)
DMA I/O Type
00: 8-bit
01: 16-bit
10: 32-bit
11: reserved
0
16
20
15
11
10
9
8
7
6
1 2 3 4 5
12
FIGURE 8.9 PROGRAMMING DMA CONTROLLER MODE REGISTER
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