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參數資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數： | 39/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-39-
Publication Release Date: 10/07/97
8.6 IEEE 1284 Parallel Port
8.6.1 Parallel Port (Host Side) Register Definition
1. Data Register (offset 378) R/W
0
7
This is the standard parallel port data register. Writing to this register in Standard mode shall drive data
to the parallel port data lines. In all other modes the drivers may be tri-stated by setting the direction bit in
the dcr register. Read to this register return the value on the data lines.
Standard mode:
write data_reg: cpu_data[0:7]
→
data_reg[0:7]
→
PAD_ED[0:7]
read data_reg: data_reg[0:7]
→
cpu_data
PS/2 mode, forward:
write data_reg: cpu_data
→
data_reg
→
PAD_ED
read data_reg: data_reg
→
cpu_data
PS/2 mode, reverse:
write data_reg: cpu_data
→
data_reg
read data_reg: PAD_ED
→
cpu_data
Centronix Peripheral mode:
read data_reg: PAD_ED
→
cpu_data
Other mode:
write data_reg: cpu_data[0:7]
→
data_reg[0:7]
read data_reg: undefined
2. DSR register (offset 379) Read only
0
7
This read-only register reflects the inputs on the parallel port interface.
Bit [0]- nBusy:
inverted parallel port
Busy
signal
Bit [1]- nAck:
parallel port
nAck
signal
Bit [2]- PError:
parallel port
PError
signal
Bit [3]- Select:
parallel port
Select
signal
Bit [4]- nFault:
parallel port
nFault
signal
Bit [5:7]- reserved
3. DCR register (offset 37a) R/W
0
7
This register directly controls several output signals as well as enabling some functions. The drivers for
nStrobe, nAutoFd, nInit, and nSelectIn are open-collector in standard mode.
Bit [0:1]- reserved
Bit [2]- Direction
0: forward (default)
Drivers are enabled.
1: reserved
In Standard mode or Parallel FIFO mode, this bit is forced to 0. The drivers are enabled,
i.e. the data pins of the parallel port are always outputs. Otherwise, this bit tri-states the
data output drivers, so that data will be read from the peripheral.
Bit [3]- ackIntEn
1: Enable an interrupt on the rising edge of nAck.
0: Disable the nAck interrupt (default)
Bit [4]- SelectIn; is inverted and then driven as parallel prot nSelectIn (default 1).
Bit [5]- nInit; is driven as parallel port nInit (default 1).
Bit [6]- autofd; is inverted and then driven as parallel port nAutoFd (default 0).
In centronic peripheral mode, when the nAck is active, the bit will be cleared by hardware.
Bit [7]- strobe; is inverted andhen driven as parallel port nStrobe (default 0).
4. ECR register (offset 243) (R/W)
0
7
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