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參數資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數： | 31/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-31-
Publication Release Date: 10/07/97
8.2 Memory Controller Registers
The addresses of all the megacell registers in W90100 are defined by a base value plus an offset
value. The base value is specified by the base register BASE[0:19], which is at the absolute address
0xF0000000. The default value of the BASE register is 0x00000000. The offset value [20:29] is defined by
each megacell.
Memory controller register :
In Memory Controller, two IO ports are used to access the entire register set: the index port is at
address
22h
and the data port is at address
23h
. To access a register, first write the index into the index port and
then read or write the data through the data port.
8.2.1 DRAMcontroller registers
The DRAM controller can interface directly to the Fast Page Mode DRAM or EDO type DRAM. And
there can be upto four banks of DRAM installed. The internal register for the DRAM controller is listed as
follows:
Index
20h
21h
22h
23h
24h
25h
26h
27h
The registers 20~27 has no default value.
Also, the base address must be set according to the bank size boundary value
28h
[0:7]
[0:1] DRAM bank 3 type : 00
→
256K, 01
→
1M, 10
→
4M, 11
→
16M,
[2:3] DRAM bank 2 type : 00
→
256K, 01
→
1M, 10
→
4M, 11
→
16M,
[4:5] DRAM bank 1 type : 00
→
256K, 01
→
1M, 10
→
4M, 11
→
16M,
[6:7] DRAM bank 0 type : 00
→
256K, 01
→
1M, 10
→
4M, 11
→
16M,
Default 256K type.
29h
[0:7]
[0] reserved(default 0)
[1] Enable DRAM bank 3.(default 0)
[2] Enable DRAM bank 2.(default 0)
[3] Enable DRAM bank 1.(default 0)
[4] Enable DRAM bank 0.(default 0)
[5] Disable DRAM address range from A0000 to FFFFF.(default 0)
[6] Fast write mode enable.(default 0)
[7] EDO fast page mode enable.(default 0)
2ah
[0:7]
[0:1] RAS# precharge time.(default 0)
[2] CAS# precharge time.(default 0)
[3] Write cycle CAS# pulse width.(default 1)
[4:5] Read cycle RAS# to CAS# delay.(default 'b01)
[6:7] Write cycle RAS# to CAS# delay.(default 'b01)
2bh
[0:7]
[0:1] Refresh period.
00 :
→
15us. (default).
01 :
→
30us.
10 :
→
60us.
11 :
→
disable refresh (for test only).
[2] Refresh cycle. RAS# active pulse width after CAS# disactive.
[3:4] Refresh cycle. RAS# active to CAS# inactive delay.(default 'b01)
[5] Refresh cycle. CAS# active to RAS# active delay.(default 0)
[6:7] Read cycle CAS# pulse width.(default 'b01)
TABLE 8.7 W90100 DRAM CONTROLLER REGISTERS
Bit No.
[0:7]
[0:3]
[0:7]
[0:3]
[0:7]
[0:3]
[0:7]
[0:3]
Description
DRAM bank 0 base address register[0:7]
DRAM bank 0 base address register[8:11]
DRAM bank 1 base address egister[0:7]
DRAM bank 1 base address register[8:11]
DRAM bank 2 base address register[0:7]
DRAM bank 2 base address register[8:11]
DRAM bank 3 base address register[0:7]
DRAM bank 3 base address register[8:11]
8.2.2 ROMcontroller registers
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