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參數資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數： | 46/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-46-
Publication Release Date: 10/07/97
8.7 Frame Memory Reduction Module Registers
There are two control registers which must be loaded to operate any of the CODEC
'
s: the Control
Register and the Byte Count Register. Other registers are used depending on the compressor or
decompressor selected. In addition, the DMA controller must be programmed to provide the input data, and to
save the output data if the output is to be transferred to memory. If the output is to go to the Video
Interface/RET, that module must be programmed as well.
The Control and Byte Count Registers are shown in Table 8.11. Both are Read/Write Registers.
NAME
CONTROL
SCAN LINE
BYTE COUNT
TABLE 8.11 CONTROL. SCAN LINE, AND BYTE COUNT REGISTERS
OFFSET
FUNCTION
Reset
1000
1004
1008
Unused
Unused
Unused
Destination
Select
Scan Line Length
Byte Count
8.7.1 Control Register
8.7.1.1 Reset Bit
The Reset Bit is bit 27 in the Control Register. When set to ONE, the CODEC
s
are reset to their
power on state (except for the Control Register.) This is intended to be used only to recover from a drastic
error. For normal operation, this bit should always be ZERO.
8.7.1.2 Destination Bit
Bit 28 in the Control Register selects the destination of the CODEC output. When this bit is ZERO,
output from the CODEC is transferred to memory. The DMA controller must be programmed for successful
transfer. If this bit is ONE, the CODEC output goes to the Video Interface/RET; in this case the RET must be
programmed for the desired function(s.)
8.7.1.3 Select Field
Bits 29 through 31 select the CODEC to be used as follows: (X = Don
t Care)
SELECT
FIELD
0XX
100
101
110
111
FUNCTION
None
Byte Compressor
Byte Decompressor
JBIG Compress/Decompress
Zero Compressor
When a CODEC completes its operation, it sets the proc_done signal and stops. In order to restart
the same, or to start a different, CODEC, the CPU must first reset bit 29 of the Control Register, and secondly
re-select a CODEC.
8.7.2 Byte Count Register
The Byte Count Register, shown in Table 8.11, is a 24-bit down-counter. It decrements as each byte
is transferred from the CODEC to the FIFO. When the counter reaches ZERO, no more data is transferred to
the FIFO. This counter must be loaded, before a CODEC is started, with a value at least as large as the
number of output bytes.
When compressing data, the counter can be loaded with a large value. After compression, the
counter can be read to determine the number of compressed bytes.
During decompression, the counter can be loaded with the expected number of output bytes to limit
the output.
8.7.3 Scanline Length Register
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