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參數(shù)資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數(shù)： | 40/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-40-
Publication Release Date: 10/07/97
Bit[0:2]- mode (R/W)
000: Standard parallel port mode (default).
In this mode, FIFO is reset and common collector drivers are used on the control lines
(nStrobe, nAutoFd, nInit, and nSelectIn). Direction bit is cleared to "0".
001: PS/2 parallel port mode
The direction could be forward or reverse. In reverse direction, reading the data register
returns the value on the data lines not the value in the data register.
010: Parallel port FIFO mode
This is the same as Standard parallel port mode except that Pwords are written or
DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel
port protocol. Note that this mode is only useful when the direction bit is 0.
011: ECP parallel port mode
In the forward direction, Pwords is placed into the FIFO and transmitted automatically to
the peripheral using ECP protocol. In the reverse direction, bytes are moved from the
ECP data port and packed into Pwords in the FIFO. All drivers have active pull-ups.
100: Centronic peripheral mode
In this mode, the parallel port acts as a reverse port in centronics mode and the direction
bit is forced to 1. The nAutofd bit (DCR bit 6) is cleared, nAck is active until nAutofd bit
(DCR bit 6) is set to 1 by software. And the parallel port data will be latched in the data
register.
101: Reserved
110: Test mode
In this mode, the FIFO may be read or written, but the data will not be transmitted on the
parallel port. Using this mode to test the depth of the FIFO, the write-threshold, and the
read-threshold.
111: Configuration mode
In this mode, the CNFGA and CNFGB registers are accessible at addresses 244 and
246
Bit[3]- nErrIntrEn (R/W, Valid only in ECP mode)
1: Disable the interrupt generated on the asserting edge of nFault (default).
0: Enables an interrupt pulse on the high to low edge of nFault.
Note that an interrupt pulse will be generated if nFault is asserted and this bit is written from a
"1" to a "0". This prevents interrupts from being lost in the time between the read of the ecr
and the wrtie of the ecr.
Bit[4]- dmaEn (R/W)
1: Enables DMA, DMA starts when serviceIntr (bit 5) is 0.
0: Disables DMA unconditionally (default).
Bit[5]- serviceIntr (R/W)
1: Disables DMA and all of the service interrupts (default).
0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts
has occurred, serviceIntr bit shall be set to a "1" by the hardware. Writing this bit to a "1"
will not cause an interrupt.
case 1: dmaEn = 1
During DMA (this bit is set to a 1 when terminal count is reached)
case 2: dmaEn = 0, direction = 0
This bit shall be set to 1 whenever there are writeIntrThreshold or more Pwords free
in the FIFO.
case 3: dmaEn = 0, direction = 1
This bit shall be set to 1 whenever there are readIntrThreshold or more valid Pwords
to be read from FIFO.
Bit[6]- Full (Read only)
1: direction = 0 The FIFO cannot accept another Pword.
1: direction = 1 The FIFO is completely full.
0: direction = 0 The FIFO has at least 1 free Pword
0: direction = 1 The FIFO has at least 1 free byte.
Bit[7]- empty (Read only)
1: direction = 0 The FIFO is completely empty
1: direction = 1 The FIFO contains less than 1 Pword of data
0: direction = 0 The FIFO contains at least 1 byte of data
0: direction = 0 The FIFO contains at least 1 Pword of data
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