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參數(shù)資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數(shù)： | 21/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-21-
Publication Release Date: 10/07/97
7.7 Image Enhancement Module
7.7.1 Setup
Setup requirements consist of programming the control registers and downloading LUT
(look_up_table) information into LUT memory. All internal register and memory locations can be read by the
host CPU to check status and/or hardware integrity.
In addition to the LUT memory and control registers, the
Line Store memory can be written and read for testing. The memory map for the control registers and internal
memories are:
Memory Map
From (PA15:0)
To (PA15:0)
Internal LUT (256 x 8)
0000
01FF
Control Registers (5 x 16)
0400
040F
Line Store Memory (4K x 16)
4000
5FFF
POWER-UP CONDITIONS:
Control Registers are powered up in their inactive state. In order to make any mode operational,
specific values must be written to the control registers as well as the LUT
'
s, which will be powered up in a
random state.
LOOK-UP TABLES:
Look-up tables are required to be loaded by the CPU. Final tables will be provided after
characterization on a sampling of representative engines.
LINE MEMORY SIZE:
Line store memory is organized as 4K words. This is segmented by the hardware architecture
according to what operating mode is selected.
MODE
600x600x1
300x300x1
200x200x1
200x100x1
1200x1200x1
600x600x8
300x300x8
BUFFERS
8
16
16
16
4
NOT BUFFERED
1
7.7.2 Margin Offset Control:
Control register
C
contains the 11 bit register that sets the left-hand margin position of the image. The
count will reflect the amount of 600dpi positions (1/600
”
) from the selected edge of the beam detect (BD)
signal, regardless of the mode selected.
7.7.3 Vertical Margin Control
The top of page detection is controlled by fsync_en (frame synch enable - control register
A,
bit 10)
and frame sync, (fsynch). Fsync_en is set by software to begin a page (lsynch’
s
will be ignored until the fsynch
signal is received). When fsync_en is high we wait for fsynch to go high and then lsynch clocks will begin
counting the vertical margin counter. When the vertical margin counter equals the vertical margin top register,
(control register
E
) data transfer will begin. The vertical margin counter will continue to increment on each
hysnc and when it reaches the value set in the vertical margin bottom register, (control register
F
) data transfer
will terminate for the remainder of the page. The CPU is required to reset fsync_en after it has moved the all of
the line data into the W90100 chip and allowed it to image that data. (one, two, or three additional lines
depending on mode). The CPU will then set fsync_en again to prepare the fsynch logic for the next page
synch signal, fsynch.
7.7.4 Input Ports
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