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參數資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數： | 6/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-6-
Publication Release Date: 10/07/97
2. W90100 Features
PA-RISC architecture
PA-RISC 1.1 third edition instruction set
PA-RISC level zero implementation
Support PA-RISC Multimedia Extension 1.0 instruction set
W90K binary compatible for user software
High-performance, singlesaclar implementation
Five-stage pipeline
Precise, efficient handling of pipeline stalls and exceptions
Delayed branch with static branch prediction
Forward: not taken; Backward: taken
One-cycle stall when prediction is wrong
Load Scheduling
Both load and store can be queued when miss
Load/store single cycle execution after previous miss
On-chip cache memory
Internal I-cache: Direct mapped, 4 KB cache (256 entries, four words/entry)
Wrap around fetching when cache miss; Cache freeze capability
Internal D-cache: 2-way set associative, 2 KB cache (2
Write-back cache with write buffer; Write-through option
New line send to CPU before dirty line write back
64 entries, 4words/entry)
Enhanced debug capability
Debug SFU supports both instruction breakpoint and data breakpoint
Two sets of instruction breakpoint regiters are provided (Mask and Offset)
Two sets of data breakpoint regiters are provided (Mask and Offset)
JTAG TAP controller for JTAG ICE support
IEEE 1149.1 JTAG boundary scan
High on-chip integration and simple I/O interface
Memory controller to interface with DAM, ROM, FLASH, and DPI interface
Support both Fast-Page mode and EDO DRAM
Upto 4 banks of DRAM, 64M Bytes per bank
Support 8-bit, 16-bit, and 32-bit ROM
Upto 4 banks of ROM or FLASH, 4M Bytes per bank
Internal 2-channel 16-bit DMA controller
Serial port with FIFO
IEEE 1284 parallel port for input
IEEE 1284 parallel port for output
8-bit Programmable I/O port
Two 24-bit timer/counters
Image Enhancement Technology
Edge enhancement as well as 1 bit and 8 bit grayscale enhancement to enhance the output print
quality.
PowerBand
Frame Memory Reduction
Built-in CODEC
'
s to reduce the system memory requirements by up to 8X in printer applications.
Direct Generic Printer Engine Interface
Economy mode: Power down and toner saver modes for economical operation
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