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參數資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數： | 44/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-44-
Publication Release Date: 10/07/97
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Note : 1. Bit [0:1] = 00 : PWord = 8 bits.
01 : reserved (8 bits).
10 : PWord = 32 bits.
11 : reserved (8 bits).
---------------------------------------------------------------------------------------
: e : IIR : - Interrupt Ident. Register. :
: : : - Read only . :
: : : :
: : : * bit 2 : "TC" interrupt occurs. (1/0 - True/False) :
: : : * bit 3 : "Address" interrupt occurs. (1/0 - True/False) :
: : : * bit 4 : "servIntr" interrupt occurs. (1/0 - True/False) :
: : : * bit 5 : "nSelectIn" interrupt occurs. (1/0 - True/False) :
: : : * bit 6 : "nInit" interrupt occurs. (1/0 - True/False) :
: : : * bit 7 : "nStrobe" interrupt occurs. (1/0 - True/False) :
---------------------------------------------------------------------------------------
Note : 1. bit 2 : Irpt_TC will be set when TC is active, and will be clear when TC
is reset (write a 0 into DMA mod_reg[4] will reset TC).
2. bit 3 : Irpt_Addr will happen only in receiver mode when PPI port receive
Address(command) bytes.
And the interrupt will be cleared when CPU reads DSRB.
3. bit 4 : Irpt_SERV will occurs if DCRB[4]= 1 and
(1) if DCRA[2]=0 and Read-threshold is reached, under this condition,
Irpt_SERV will keep high till the above condition is dismissed.
(2) if DCRA[2]=1 and the DFifo is from non-empty to empty status,
a two system-clock-cycle Irpt_SERV will be issued.
4. bit 5 : Irpt_NSELI will occurs if DCRB[5]= 1 and a H-to-L or L-to-H
transistion is activated on "nSelectIn".
And it will be cleared when CPU read DSRA.
5. bit 6 : Irpt_NINIT will occurs if DCRB[6]= 1 and a H-to-L or L-to-H
transistion is activated on "nInit".
And it will be cleared when CPU read DSRA.
6. bit 7 : Irpt_NSTB will occurs if DCRB[7]= 1 and a H-to-L
transistion is activated on "nStrobe".
And it will be cleared when CPU read DSRA.
---------------------------------------------------------------------------------------
: f : DR : - Data Register. :
: : : - Read only. (optional) :
: : : :
: : : * bit [0:7] : Data port input latch. :
---------------------------------------------------------------------------------------
Note : 1. Reading DR returns the value on the data-register but not the value in the
data-line.
2. DR works only in forward transfer mode, and it latchs data-line's state
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