
W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-22-
Publication Release Date: 10/07/97
The data input is parallel, eight bit. Data is transferred into the design on the rising edge of the parallel
video clock. The first clock after the hysnc signal will transfer the first eignt bits of data into the design.
7.7.5 Look-Up Table Memory (LUT):
To Load or Read the LUT memory the following bit in control register
A
must be set:
CPU2InternalLUT
= Load LUT Memory (512x10)
Subsequent reading or writing to memory locations 0000-03FF will address the LUT memory, Data Bit
0 = LUT Bit 0.
What are LUT
'
s for
Look-up tables translate the fixed image values that are affected by engine
linearity, temperature, aging, environmental, toner exhaustion, and other variables as well as features such as
toner saver, paper type, type of input, etc. into values that will reproduce the highest quality image possible.
The number of variables that influence the printed image are numerous and in order to correctly image the job
these variables have to be compensated for. This is the job of the LUT memory..
7.7.6 OPERATING MODES
7.7.6.1 1200x1200x1
1200 Mode is selected by programming control register
A
bits [3:0] with a 1010. Source
data must be in the two line format that can be used. The two line format requires that two lines of 1200 data
must be transferred for each hysnc received by the design. The design will transfer two lines of sequential
1200 data per hysnc. The length of the lines is tracked via the line length register value (control register
D
,
[11:0]) and when it reaches the programmed count it repeats the count for the second line. The CPU must
program the line length (control register
D
) with the length of a single line of 1200 data into the Image
Enhancement module.
To set up the W90100 for 1200 Enhanced the LUT memory must be loaded and the
following control registers must be programmed:
Control Register
A
Mode
Mfunction
(see table 2.0)
vidkill
bdedge (0 = rising edge, 1 = falling edge)
vidpol (0 = normal, 1 = inverse)
fsync_en (see paragraph for operational desc)
Unused
Other
BITS
[3:0]
[6:5}
7
8
9
10
[12:11]
4, 13, 14, 15
VALUE
1010
XX
1
0 or 1
0 or 1
0 or 1
00
0,0,0,0
Control Register
B
Unused
BITS
[15:0]
VALUE
00h
Other Control Registers
C: Horizontal Margin Register
C: Line Synch Width Register
D: Line Length Register
D: Unused
E: Vertical Margin (Top) Register
F: Vertical Margin (Bottom) Register
BITS
[10:0]
[15:11}
[11:0]
[15:12]
[15:0]
[15:0]
VALUE
0 - 3FFh
0 - 1Fh
0 - FFFh
0000
0 - FFFFh
0 - FFFFh
7.7.6.2 600x600x1
600 Mode is selected by programming control register
A
,bits [3:0]. There are four different
600x1 operating modes to choose from. 0h is selected for enhanced text only, 1h is the test mode for 0h. 2h
is for enhanced text and enhanced one bit gray scale. 3h is for unenhanced text and enhanced one bit gray
scale. The CPU must program the line length (Control Register
D
) of a single line of 300 data into the
Winbond chip.