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參數(shù)資料
型號： W90100F
廠商： WINBOND ELECTRONICS CORP
英文描述： Embedded Micro-Controller(32位嵌入式的微控制器)
中文描述： 嵌入式微控制器（32位嵌入式的微控制器）
文件頁數(shù)： 26/61頁
文件大?。?/td> 380K
代理商： W90100F
W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-26-
Publication Release Date: 10/07/97
8. Control and Status Register
8.1 CPU Registers
The W90100 CPU core implements all the registers needed for a Level 0 processor as defined in the
PA-RISC specifications. Some registers or register bits are not needed in a Level 0 processor and are defined
as nonexistent registers or register bits. The W90100 CPU implements three AIRs (Architecture Invisible
Registers) that can be accessed by executing DIAG instructions.
8.1.1 General registers
Thirty-two 32-bit general registers provide the central resource for all computation. They are
numbered GR 0 through GR 31, and are available to all program at all privilege levels. GR 0, when referenced
as source operand, delivers zeros. When GR 0 is used as destination, the result is discarded. GR 1 is the
target of the ADD IMMEDIATE LEFT instruction. GR 31 is the instruction address offset link register for the
base relative interspace procedure call instruction. GR 1 and GR 31 can also be used as general register.
0
31
GR 0
GR 1
GR 2
Permanent zero
Target for ADDIL or General use
General use
General use
Link register for BLE or General use
GR 30
GR 31
FIGURE 8.1 GENERAL REGISTERS
8.1.2 Shadow registers
W90100 CPU core provides seven registers called shadow registers as defined in the PA-RISC
architecture. The contents of GR1,8,9,16,17,24 and 25 are copied upon interruptions. Shadow registers
reduce the state save and restore time by eliminating the need for general register saves and restores in
interruption handlers. The behavior of the shadow registers is described below.
Before entering interrupt routine:
Contents of seven general registers are copied into shadow registers in
one cycle.
When executing RFIR:
Contents of shadow registers are copied into general registers automatically in
one cycle.
8.1.3 Processor Status Word (PSW)
The processor state of W90K is encoded in a 32-bit register called the Processor Status Word
(PSW). The format of PSW is shown in figure 8.2. The old value of the PSW is saved in the Interrupt
Processor Status Word (IPSW) when interruption occurs. The PSW is set to the contents of the IPSW by the
RFIR (RETURN FROM INTERRUPTION and RESTORE) instruction.
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