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參數資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數： | 32/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-32-
Publication Release Date: 10/07/97
In Memory Controller, two IO ports are used to access the entire register set: the index port is at
address
22h
and the data port is at address
23h
. To access a register, first write the index into the index port
and then read or write the data through the data port.
The ROM controller can interface to either ROM or FLASH memory. Any write to ROM has no
effect at all. The FLASH memory can be read or written through the control of
oe_
or
we_
signals. The internal
register for the ROM controller is listed as follows:
ROM controller register :
Bit No.
Description
[0:7]
ROM bank 0 base address register[0:7]
[0:7]
ROM bank 0 base address register[8:15]
[0:7]
ROM bank 1 base address register[0:7]
[0:7]
ROM bank 1 base address register[8:15]
[0:7]
ROM bank 2 base address register[0:7]
[0:7]
ROM bank 2 base address register[8:15]
[0:7]
ROM bank 3 base address register[0:7]
[0:7]
ROM bank 3 base address register[8:15]
The register 0~7 has no default value.
[0:7]
[0:3] ROM bank 0 size.
[4:7] ROM bank 1 size.
[0:7]
[0:3] ROM bank 2 size.
[4:7] ROM bank 3 size.
0XXX
→
disable.
1000
→
64K, 1001
→
128K, 1010
→
256K, 1011
→
512K,
1100
→
1M, 1101
→
2M, 1110
→
4M, 1111
→
16M.
The default value is 0.
[0:7]
[0:1] bank 3 band width: 00
→
8_bit, 01
→
16_bit, 10
→
32_bit, 11
→
reserved
[2:3] bank 2 band width: 00
→
8_bit, 01
→
16_bit, 10
→
32_bit, 11
→
reserved
[4:5] bank 1 band width: 00
→
8_bit, 01
→
16_bit, 10
→
32_bit, 11
→
reserved
[6:7] bank 0 band width: 00
→
8_bit, 01
→
16_bit, 10
→
32_bit, 11
→
reserved
The default width of bank 0~3 is set by memory data bus bit 30 and 31.
[0:7]
[0:2] ROM access wait state.
000
→
wait 2 state. 001
→
wait 3 state.
010
→
wait 4 state. 011
→
wait 5 state.
100
→
wait 6 state. 101
→
wait 7 state.
110
→
wait 8 state. 111
→
wait 9 state.
The default wait state is 9.
[3] access ROM bank0 only. Default bank0 only.
[4] LA mode. Default LA mode.
TABLE 8.8 W90100 ROM CONTROLLER REGISTERS
Index
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0ah
0bh
8.2.3 DPI interface
The DPI interface can interface to Digital Product
'
s expansion card. The Base register define the
base address. Each segment is 128K. The address space from base+0 to base+
ffffh
is for the 64K memory
on the expansion card. The address base+10000h and base+10001h are addresses for registers on the
expansion card. The address above base+10002 is not used.
DPI interface register :
Bit No.
[0:7]
[0:6]
[0:7]
[0:6]
Index
10h
11h
12h
13h
Description
Ext_BUS 1 base address register[0:7]
Ext_BUS 1 base address register[8:14]
Ext_BUS 2 base address register[0:7]
Ext_BUS 2 base address register[8:14]
The register 10~13 has no default value.
[0] Ext_Bus card detect bit. 1: card exist, 0: card not exit. (read only)
[1] Ext_Bus base address 1 enable. (default 0)
[2] Ext_Bus base address 2 enable. (default 0)
TABLE 8.9 W90100 DPI INTERFACE CONTROLLER REGISTERS
148h
[0:2]
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