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參數(shù)資料
型號(hào)： W90100F
廠商： WINBOND ELECTRONICS CORP
英文描述： Embedded Micro-Controller(32位嵌入式的微控制器)
中文描述： 嵌入式微控制器（32位嵌入式的微控制器）
文件頁數(shù)： 43/61頁
文件大小： 380K
代理商： W90100F
W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-43-
Publication Release Date: 10/07/97
Note : 1. Bit [4:5] = 00 : The TOP PWord contained a complete PWord.
01 : The TOP PWord contained 1 valid byte.
10 : The TOP PWord contained 2 valid byte.
11 : The TOP PWord contained 3 valid byte.
2. Bit 6 : This bit once be set, it will keep in set-state until the fifo is
reseted.
2. Bit 7 : This bit once be set would prevent from the following parallel-port-
interface access.
Read DSRB register would clear the bit.
---------------------------------------------------------------------------------------
: c : DCRB : - Device Control Register B :
: : : - Read/Write. :
: : : :
: : : * bit 0 : Dma mode enable (and request DMA). (1/0 - Enable/Disable) :
: : : * bit 1 : Reset FIFO. (1/0 - Enable/Disable) :
: : : * bit 2 : Reset Device. (1/0 - Enable/Disable) :
: : : * bit [3:5] : Device mode select. :
: : : * bit [6:7] : Fifo read-threshold. :
---------------------------------------------------------------------------------------
Note : 1. Bit 0 : A low-to-high transistion in this bit will activate DREQ,
and DREQ will be deasserted when DMAC reponses DACK.
This bit will also be cleared by a DMA TC (terminal count).
2. Bit [1:2] : It is a self-clear bit. Writing a logical 1 will generate 1 SCLK
period high "reset" signal.
3. Bit [3:5] = 000 : Bidirectional Standard Parallel Port Mode (SPP).
001 : Fast reverse Standard FIFO Mode (FSPP).
010 : ECP mode.
011 : EPP mode.
1xx : reserved
4. Bit [6:7] = 00 : Read Threshold = 16 byte
01 : Read Threshold = 12 byte
10 : Read Threshold = 8 byte
11 : Read Threshold = 1 byte (if PWord = 1 or 2 byte).
Read Threshold = 4 byte (if PWord = 4 byte).
---------------------------------------------------------------------------------------
: d : DCRC : - Device Control Register C :
: : : - Read/Write. :
: : : :
: : : * bit [0:1] : PWord size select. :
: : : * bit 2 : "TC" interrupt enable. (1/0 - Enable/Disable) :
: : : * bit 3 : "Address" interrupt enable. (1/0 - Enable/Disable) :
: : : - bit 4 : "servIntr" interrupt enable. (1/0 - Enable/Disable) :
: : : - bit 5 : "nSelectIn" interrupt enable. (1/0 - Enable/Disable) :
: : : - bit 6 : "nInit" interrupt enable. (1/0 - Enable/Disable) :
: : : - bit 7 : "nStrobe" interrupt enable. (1/0 - Enable/Disable) :
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