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參數(shù)資料
型號(hào)： W90100F
廠(chǎng)商： WINBOND ELECTRONICS CORP
英文描述： Embedded Micro-Controller(32位嵌入式的微控制器)
中文描述： 嵌入式微控制器（32位嵌入式的微控制器）
文件頁(yè)數(shù)： 50/61頁(yè)
文件大小： 380K
代理商： W90100F
W90100F
Printer Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
-50-
Publication Release Date: 10/07/97
FFFmc:
This field is set to ONE if a private FMC was inserted into the code during encoding. This
feature is controlled by CtlJbig-JLimits (q.v..)
ZeroOver:
This bit indicates an internal coder error.
Line1:
This bit is set to ONE if the coder is coding the first image line. It is required for Speedmarks.
Line2:
This bit is set to ONE if the coder is coding the first or second image line. It is required for
Speedmarks.
RenShift:
This field indicates the renormalization status of the JBIG base and interval registers. It is
required for Speedmarks.
8.7.4.14 StatusJ7 Register
This read-only register is useful for testing, determining the status of operation on the current image,
and for Speedmarks.
Done:
This bit is set when the current operation is complete or has been terminated by an error. It is
cleared when the JBIG coder is not selected.
NewLen:
This bit is set if a NEWLEN FMC was received. If it is set, the Lines parameter may have
been changed to give the new image length. If it is ZERO, the image size is left as programmed.
Init:
This bit is set while CxRam is being initialized, and ZERO thereafter. CxRam access is prohibited
when Init = 1.
Error:
If DONE = 1 and this field is not ZERO, an error has occurred during processing. The possible
error values are as follows:
ERROR
0
1
1
1
2
3
4
5
6
7
INTERPRETATION
No error
Private FMC
Invalid Escape Code
ABORT FMC
Non-zero AT FMC yAT
AT FMC Tx < 0
Non-zero AT FMC Ty
NEWLEN FMC Yd > 64K
Comment Ld > 64K
Missing End-of-Stripe
8.7.4.15 JRomHi Register
A state transition ROM is used to determine the information associated with a given coding state. This
ROM data is made accessible for testing purposes via the registers JRomHi and JRomLo. Access to this data
involves the following steps:
1. The CODEC must be deselected; see Section 8.7.1.3.
2. Either the JDecode or the JEncode bit, but not both, should be set in CtlJbig.
3. The State0 field in CxRam is must be loaded with the desired ROM address. The
allowed addresses are 0-112 decimal.
4. Finally, the register is read to get the data.
LpsInt:
This number is the next interval value when the less probable symbol is received. It
corresponds to the ISO IS 115454 variable LSZ.
8.7.4.16 JRomLo Register
See section 8.5.7.15 on how to read this register.
LpsState:
This field gives the next context state for renormalizations when the less probable symbol is
received.
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