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參數資料
型號： W83877AF
廠商： WINBOND ELECTRONICS CORP
元件分類： 外設及接口
英文描述： Multi-Function I/O Port Controller(多功能輸入／輸出口控制器)
中文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封裝： QFP-100
文件頁數： 105/171頁
文件大小： 1634K
代理商： W83877AF
W83877AF
Publication Release Date: Dec. 1996
Preliminary Version 0.52
- 103 -
5.7 Joystick Mode
(Patent pending)
The joystick mode allows users to plug a joystick into the parallel port DB-25 connector. The pin
definitions are shown in Table 5-1.
Pins NSTB
,
AFD
,
NSLIN
,
and
INIT
output high as a voltage supply to the joystick.
Pins PD5 and PD4 are the button input of the joystick.
Pins PD1 and PD0 are the X/Y axis paddle input of the joystick.
There are two one-shot timers (556) inside the W83877AF for use with the joystick.
6.0 GAME PORT DECODER
The W83877AF provides
GMRD
and
GMWR
pins that decode game port address as specified in
CR1E and I/O read/write commands.
If the host issues
IOR
and the specified address, the
GMRD
pin is
low active; if it issues
IOW
and the
specified address, the
GMWR
pin is low active.
7.0 PLUG AND PLAY CONFIGURATION
A powerful new plug-and-play function has been built into the W83877AF to help simplify the task of
setting up a computer environment. With appropriate support from BIOS manufacturers, the system
designer can freely allocate Winbond I/O devices (i.e., the FDC, PRT, UART, IDE, and game port) in
the PC's I/O space (100H - 3FFH). In addition, the W83877AF also provides 8 interrupt requests and
3 DMA pairs for designers to assign in interfacing FDCs, UARTs, and PRTs. Hence this powerful I/O
chip offers greater flexibility for system designers.
The PnP feature is implemented through a set of Extended Function Registers (CR1E and CR20 to
29). Details on configuring these registers are given in Section 8. The default values of these PnP-
related registers set the system to a configuration compatible with environments designed with
previous Winbond I/O chips.
8.0 EXTENDED FUNCTION REGISTERS
The W83877AF provides many configuration registers for setting up different types of configurations.
After power-on reset, the state of the hardware setting of each pin will be latched by the relevant
configuration register to allow the W83877AF to enter the proper operating configuration. To protect
the chip from invalid reads or writes, the configuration registers cannot be accessed by the user.
There are four ways to enable the configuration registers to be read or written. HEFERE (CR0C bit 5)
and HEFRAS (CR16 bit 0) can be used to select one out of these four methods of entering the
Extended Function mode as follows:
相關PDF資料
PDF描述
W83877ATD enhanced version from Winbonds most popular I/O chip W83877F
W83877ATF enhanced version from Winbonds most popular I/O chip W83877F
W83877 WINBOND I/O
W83877F WINBOND I/O
W83877TD I/O chip disk drive adapter
相關代理商/技術參數
參數描述
W83877ATD 制造商:WINBOND 制造商全稱:Winbond 功能描述:enhanced version from Winbonds most popular I/O chip W83877F
W83877ATF 制造商:WINBOND 制造商全稱:Winbond 功能描述:enhanced version from Winbonds most popular I/O chip W83877F
W83877F 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O
W83877TD 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O
W83877TF 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O
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