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參數(shù)資料
型號: W83877AF
廠商: WINBOND ELECTRONICS CORP
元件分類: 外設及接口
英文描述: Multi-Function I/O Port Controller(多功能輸入/輸出口控制器)
中文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封裝: QFP-100
文件頁數(shù): 21/171頁
文件大小: 1634K
代理商: W83877AF
W83877AF
Publication Release Date: Dec. 1996
Preliminary Version 0.52
- 19 -
2.0 FDC FUNCTIONAL DESCRIPTION
2.1 W83877AF FDC
The floppy disk controller of the W83877AF integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to data rate 1 M bits/sec. (2 M bits/sec for fast tape drive with 48 MHz crystal
in)
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
2.1.1 AT interface
The interface consists of the standard asynchronous signals: RD , WR, A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
2.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
and DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The
advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors.
The following tables give several examples of the delays with a FIFO. The data are based upon the
following formula:
THRESHOLD
×
(1/Data Rate) *8 - 1.5
μ
S = DELAY
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 500K BPS
Data Rate
1
×
16
μ
S - 1.5
μ
S = 14.5
μ
S
2
×
16
μ
S - 1.5
μ
S = 30.5
μ
S
8
×
16
μ
S - 1.5
μ
S = 6.5
μ
S
15
×
16
μ
S - 1.5
μ
S = 238.5
μ
S
1 Byte
2 Byte
8 Byte
15 Byte
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
1
×
8
μ
S - 1.5
μ
S = 6.5
μ
S
2
×
8
μ
S - 1.5
μ
S = 14.5
μ
S
8
×
8
μ
S - 1.5
μ
S = 62.5
μ
S
15
×
8
μ
S - 1.5
μ
S = 118.5
μ
S
1 Byte
2 Byte
8 Byte
15 Byte
相關PDF資料
PDF描述
W83877ATD enhanced version from Winbonds most popular I/O chip W83877F
W83877ATF enhanced version from Winbonds most popular I/O chip W83877F
W83877 WINBOND I/O
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相關代理商/技術參數(shù)
參數(shù)描述
W83877ATD 制造商:WINBOND 制造商全稱:Winbond 功能描述:enhanced version from Winbonds most popular I/O chip W83877F
W83877ATF 制造商:WINBOND 制造商全稱:Winbond 功能描述:enhanced version from Winbonds most popular I/O chip W83877F
W83877F 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O
W83877TD 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O
W83877TF 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O