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參數(shù)資料
型號: W83877AF
廠商: WINBOND ELECTRONICS CORP
元件分類: 外設(shè)及接口
英文描述: Multi-Function I/O Port Controller(多功能輸入/輸出口控制器)
中文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封裝: QFP-100
文件頁數(shù): 111/171頁
文件大?。?/td> 1634K
代理商: W83877AF
W83877AF
Publication Release Date: Dec. 1996
Preliminary Version 0.52
- 109 -
8.2.5 Configuration Register 4 (CR4), default = 00H
When the device is in Extended Function mode and EFIR is 04H, the CR4 register can be accessed
through EFDR. The bit definitions are as follows:
7 6 5 4 3 2 1 0
URBTRI
URATRI
GMTRI
PRTTRI
URBPWD
URAPWD
GMPWD
PRTPWD
PRTPWD (Bit 7):
0
1
Supplies power to the parallel port (default)
Puts the parallel port in power-down mode
GMPWD (Bit 6):
0
1
Supplies power to the game port (default)
Puts the game port in power-down mode
URAPWD (Bit 5):
0
1
Supplies power to COMA (default)
Puts COMA in power-down mode
URBPWD (Bit 4):
0
1
Supplies power to COMB (default)
Puts COMB in power-down mode
PRTTRI (Bit 3):
This bit enables or disables the tri-state outputs of parallel port in power-down mode.
0
The output pins of the parallel port will not be tri-stated when parallel port is in power-
down mode. (default)
1
The output pins of the parallel port will be tri-stated when parallel port is in power-
down mode.
GMTRI (Bit 2):
This bit enables or disables the tri-state outputs of the game port in power-down mode.
0
The output pins of the game port will not be tri-stated when game port is in power-
down mode. (default)
1
The output pins of the game port will be tri-stated when game port is in power-down
mode.
URATRI (Bit 1):
相關(guān)PDF資料
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