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參數(shù)資料
型號： W83877AF
廠商： WINBOND ELECTRONICS CORP
元件分類： 外設(shè)及接口
英文描述： Multi-Function I/O Port Controller(多功能輸入／輸出口控制器)
中文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封裝： QFP-100
文件頁數(shù)： 46/171頁
文件大小： 1634K
代理商： W83877AF
W83877AF
Publication Release Date: Dec. 1996
Preliminary Version 0.52
- 44 -
3.0 IDE
The IDE interface is essentially the AT bus ported to the hard disk drive. The hard disk controller
resides on the IDE hard disk drive. So the IDE interface provides only chip select signals and AT bus
signals between the IDE hard disk drive and ISA slot. Table 3-1 shows the IDE registers and their ISA
addresses.
Table 3-1
I/O ADDRESS
REGISTERS
OFFSET
READ
WRITE
CS0
base address + 0
Data Register
Data Register
CS0
base address + 1
Error Register
Write-Precomp
CS0
base address + 2
Sector Count
Sector Count
CS0
base address + 3
Sector Number
Sector Number
CS0
base address + 4
Cylinder LOW
Cylinder LOW
CS0
base address + 5
Cylinder HIGH
Cylinder HIGH
CS0
base address + 6
SDH Register
SDH Register
CS0
base address + 7
Status Register
Command Register
CS1 base address + 6
Alternate Status
Fixed Disk Control
3.1 IDE Decode Description
When the processor selects the addresses which match the ones specified in CR 21, the chip system
enables CS0 = LOW; otherwise, CS0 = HIGH. When the processor selects the address which
matches the one specified in CR22, the chip system enables CS1 = LOW; otherwise, CS1 = HIGH.
4.0 UART PORT
4.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half
(five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this
16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the
UARTs also include complete modem control capability and a processor interrupt system that may be
software trailed to the computing time required to handle the communication link. The UARTs have a
FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-
byte FIFOs for both receive and transmit mode.
相關(guān)PDF資料
PDF描述
W83877ATD enhanced version from Winbonds most popular I/O chip W83877F
W83877ATF enhanced version from Winbonds most popular I/O chip W83877F
W83877 WINBOND I/O
W83877F WINBOND I/O
W83877TD I/O chip disk drive adapter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W83877ATD 制造商:WINBOND 制造商全稱:Winbond 功能描述:enhanced version from Winbonds most popular I/O chip W83877F
W83877ATF 制造商:WINBOND 制造商全稱:Winbond 功能描述:enhanced version from Winbonds most popular I/O chip W83877F
W83877F 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O
W83877TD 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O
W83877TF 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O
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