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參數(shù)資料
| 型號(hào)： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)的PCI總線的S / T的接口控制器） |
| 文件頁(yè)數(shù)： | 14/98頁(yè) |
| 文件大?。?/td> | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Used to enable normal operation (1) or enter test mode (0).
PCI Power Management
Power Management Event Signal. Level triggered, active HIGH. Drive
a transistor to PME# in PCI slot.
Peripheral Control
Timer 2 output. A square wave with 50 % duty cycle, 1~63 ms period
can be generated.
A level change (either direction) will generate a maskable interrupt on
the PCI bus interrupt request pin INTA#.
A level change (either direction) will generate a maskable interrupt on
the PCI bus interrupt request pin INTA#.
When confiured as simple IO mode (PCTL:XMODE = 0), these pins
can read/write data from/to peripheral components. The pin directions
are selected via register. After hardware reset, the output drivers are
disabled.
When configured as microprocessor mode (PCTL:XMODE = 1),
address and data are multiplexed on these pins.
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the Address Latch Enable output.
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the read pulse.
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the write pulse.
Power and Ground
Digital Power Supply (5V
±
5%).
Analog Power Supply (5V
±
5%).
PCI Bus Power Supply (5V
±
5%).
Digital Ground.
Analog Ground.
PCI Bus Ground.
Publication Release Date:
Mar,2000
Revision 1.0
-14 -
TESTP
61
I
PME
60
O
TOUT2
20
O
XINTIN0
52
I
XINTIN1
53
I
IO10-IO0
79,78,77,29,28,
27,26,4,3,2,1
I/O
XAD7-XAD0
29,28,27,26,
4,3,2,1
77
I/O
XALE
O
XRDB
78
O
XWRB
79
O
VDDD
VDDA
VDDB
VSSD
VSSA
VSSB
17,58,67,83
51
6,32,43,89
16,59,68,82
48
5,31,42,88
I
I
I
I
I
I
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