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參數(shù)資料
| 型號(hào)： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)的PCI總線的S / T的接口控制器） |
| 文件頁(yè)數(shù)： | 53/98頁(yè) |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-53 -
This bit indicates a collision on the S-bus has been detected. W6692A will automatically reset the transmitter and software
must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
TIN2 Timer 2 Expiration
This bit is set when Timer 2 counts down to zero.
GCI GCI Interrupt
This bit is set when at least one bit is set in GCI_EXIR register.
ISC Indication or S Channel Change
A change in the layer 1 indication code or multiframe S channel has been detected. The actual value can be read from CIR or
SQR registers.
T1EXP Timer 1 Expiration
Expiration occurs in the Timer 1.
.
8.1.9 D_ch Extended Interrupt Mask Register
Value after reset: FFH
7
6
5
RDOV
XDUN
XCOL
Setting the bit to "1" masks the corresponding interrupt source in D_EXIR register. Masked interrupt status bits are read as
zero. They are internally stored and pending until the mask bits are zero.
All the interrupts in D_EXIR will be masked if the IMASK:D_EXI bit is set to "1".
D_EXIM
Read/Write Address 20H/08H
4
3
2
1
0
1
TIN2
GCI
ISC
T1EXP
8.1.10 D_ch Status Register
Value after reset: 00H
7
6
XDOW
0
XDOW Transmit Data Overwritten
At least one byte of data has been overwritten in the D_XFIFO. This bit is set by data overwritten condition and is cleared only
by XRST command.
XBZ Transmitter Busy
This bit indicates the D_HDLC transmitter is busy. The XBZ bit is active from the transmission of opening flag to the
transmission of closing flag.
DRDY D Channel Ready
D_XSTA
Read
Address 24H/09H
5
4
3
0
2
0
1
0
0
0
XBZ
DRDY
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