
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-69 -
CI1X6_1
Transmitted data of GCI CI1 channel. A read to these bits returns the previously written value.
Example application is data of ARCOFI's Peripheral Control Interface output pins.
8.1.46 GCI Extended Interrupt Register GCI_EXIR Read_clear
Value after reset : 00H
7
6
5
4
0
0
0
MO1C
MO1C Monitor Channel 1 Status Change
A change in the Monitor Channel 1 Interrupt register ( MO1I ) has occurred. A new Monitor channel byte is stored in the
MO1R register.
MO0C Monitor Channel 0 Status Change
A change in the Monitor Channel 0 Interrupt register (MO0I) has occurred. A new Monitor channel byte is stored in the
MO0R register.
IC1 IC1 Synchronous Transfer Interrupt
When enabled, an interrupt is generated at end of GCI IC1 time slot every GCI frame (125
μ
s).
IC2 IC2 Synchronous Transfer Interrupt
When enabled, an interrupt is generated at end of GCI IC2 time slot every GCI frame (125
μ
s).
CI1 GCI CI1 Synchronous Transfer Interrupt
When enabled, an interrupt is generated when there is a change in the received CIR1_6-1 code without double last look
criterion.
Address 76H/4AH
3
2
1
0
MO0C
IC1
IC2
CI1
8.1.47 GCI Extended Interrupt Mask Register
Value after reset: F7H
7
6
5
1
1
1
Bits 7-5 are fixed at "1" and bit 3 is fixed at '0". This means MO0C interrupt cannot be masked. The interrupt is disabled when
the bit is set.
GCI_EXIM Read/Write Address 7AH/4BH
4
3
0
2
1
0
MO1C
IC1
IC2
CI1
8.2 B1 HDLC controler
TABLE 8.3 REGISTER ADDRESS MAP: B1 CHANNEL HDLC